인터페이스 LVDS, M-LVDS 및 PECL

DS92LV16

활성

16비트 버스 LVDS 시리얼라이저/디시리얼라이저 - 25~80MHz

제품 상세 정보

Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 2560 Input signal BLVDS, LVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 2560 Input signal BLVDS, LVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PN) 80 196 mm² 14 x 14
  • 25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
  • Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
  • ±100mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.5kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

  • 25–80 MHz 16:1/1:16 Serializer/Deserializer (2.56Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation With Separate Clock, Enable, Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks To Random Data)
  • Wide +/−5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 104mA (typ) Transmitter, 119mA (typ) Receiver at 80MHz
  • ±100mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.5kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

The DS92LV16 Serializer/Deserializer (SERDES) pair transparently translates a 16–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 16-bit, or less bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback and local loopback features provide the following functionality: the local loopback enables the user to check the integrity of the transceiver from the local parallel-bus side and the system can check the integrity of the data transmission line by enabling the line loopback.

The DS92LV16 incorporates BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

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기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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7개 모두 보기
유형 직함 날짜
* Data sheet DS92LV16 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz datasheet (Rev. H) 2013/04/16
Application note DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 2013/04/29
Application note DS92LV16 Power Up Reset (Rev. B) 2013/04/26
Application note External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) 2013/04/26
Application note How to Validate BLVDS SER/DES Signal Integrity Using an Eye Mask (Rev. A) 2013/04/26
Design guide DS92LV16 16-bit SerDes Design Guide 2007/03/29
White paper Easy-to-Use LVDS Serdes for the Serdes Neophyte 2001/09/01

설계 및 개발

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시뮬레이션 모델

DS92LV16 IBIS Model

SNLM027.ZIP (18 KB) - IBIS Model
시뮬레이션 툴

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사용 설명서: PDF
패키지 CAD 기호, 풋프린트 및 3D 모델
LQFP (PN) 80 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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