DS92LV18
- 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
- Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
- Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
- Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
- Line and Local Loopback Modes
- Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
- No External Coding Required
- Internal PLL, No External PLL Components Required
- Single +3.3V Power Supply
- Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
- ±100 mV Receiver Input Threshold
- Loss of Lock Detection and Reporting Pin
- Industrial −40 to +85°C Temperature Range
- >2.0kV HBM ESD
- Compact, Standard 80-Pin LQFP Package
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The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.
The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz datasheet (Rev. E) | 2013/04/18 | |
| Application note | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013/04/29 | ||
| Application note | External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) | 2013/04/26 | ||
| User guide | 18-Bit SerDes Evaluation Kit User Manual | 2012/01/25 | ||
| Design guide | 18-bit SerDes Design Guide (DS92LV18, SCAN921821) | 2007/03/29 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
LVDS-18B-EVK — 18비트 버스 LVDS 시리얼라이저/디시리얼라이저 평가 보드(15~66MHz)
The LVDS-18B-EVK evaluation kit (EVK) is a complete kit to evaluate our 18-bit SerDes devices (DS92LV18 and SCAN921821) with low-cost twisted pair cables and other 100-Ω differential cables.
PSPICE-FOR-TI — TI 설계 및 시뮬레이션 툴용 PSpice®
TI 설계 및 시뮬레이션 환경용 PSpice는 기본 제공 라이브러리를 이용해 복잡한 혼합 신호 설계를 시뮬레이션할 수 있습니다. 레이아웃 및 제작에 (...)
TINA-TI — SPICE 기반 아날로그 시뮬레이션 프로그램
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| LQFP (PN) | 80 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
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