제품 상세 정보

Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 200 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 2.3 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 ESD HBM (typ) (kV) 2 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 9 OFF-state leakage current (max) (µA) 60 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Automotive
Protocols Analog Configuration 1:1 SPST Number of channels 8 Bandwidth (MHz) 200 Supply voltage (max) (V) 3.6 Supply voltage (min) (V) 2.3 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 3.6 ESD HBM (typ) (kV) 2 Operating temperature range (°C) -40 to 125 Input/output continuous current (max) (mA) 128 COFF (typ) (pF) 9 OFF-state leakage current (max) (µA) 60 Ron (max) (mΩ) 40000 VIH (min) (V) 2 VIL (max) (V) 0.8 Rating Automotive
VQFN (RKS) 20 11.25 mm² 4.5 x 2.5
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results: –
    • Device Temperature Grade 1: –40°C to +125°C
    • Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C5
  • Standard ’245-Type Pinout
  • 5-Ω Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified With the Following Results: –
    • Device Temperature Grade 1: –40°C to +125°C
    • Ambient Operating Temperature Range
    • Device HBM ESD Classification Level 2
    • Device CDM ESD Classification Level C5
  • Standard ’245-Type Pinout
  • 5-Ω Switch Connection Between Two Ports
  • Rail-to-Rail Switching on Data I/O Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)

The SN74CBTLV3245A-Q1 provides eight bits of high-speed bus switching in a standard ’245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature maitains that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

To maintain the high-impedance state during power up or power down, OE is tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CBTLV3245A-Q1 provides eight bits of high-speed bus switching in a standard ’245 device pinout. The low on-state resistance of the switch allows connections to be made with minimal propagation delay.

The device is organized as one 8-bit switch. When output enable (OE) is low, the 8-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature maitains that damaging current does not backflow through the device when the device is powered down. The device has isolation during power off.

To maintain the high-impedance state during power up or power down, OE is tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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기술 자료

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* Data sheet SN74CBTLV3245A-Q1 Low-Voltage Octal FET Bus Switch datasheet PDF | HTML 2026/01/16
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025/11/13
Selection guide Little Logic Guide 2018 (Rev. G) 2018/07/06
Application note How to Select Little Logic (Rev. A) 2016/07/26
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
More literature Digital Bus Switch Selection Guide (Rev. A) 2004/11/10
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004/11/04
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
User guide Signal Switch Data Book (Rev. A) 2003/11/14
Application note Bus FET Switch Solutions for Live Insertion Applications 2003/02/07
Application note Texas Instruments Little Logic Application Report 2002/11/01
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002/08/29
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
User guide CBT (5-V) And CBTLV (3.3-V) Bus Switches Data Book (Rev. B) 1998/12/01

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패키지 CAD 기호, 풋프린트 및 3D 모델
VQFN (RKS) 20 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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