SN74GTL2006
- Operates as GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
- Series Termination on TTL Outputs of 30

- Latch-Up Testing to JEDEC Standard JESD 78 Exceeds 500 mA
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
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The SN74GTL2006 is a 13-bit translator to interface between the 3.3-V LVTTL chipset I/O and the Xeon processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.
기술 자료
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| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | SN74GTL2006 datasheet | 2004. 12. 17 |