SN74GTL2007

Name: SN74GTL2007
Brand: TI
SKU: SN74GTL2007
Price: 0.978 USD

활성

12비트 GTL-/GTL/GTL+ To LVTTL 변환기

지금 주문

데이터 시트

document-pdfAcrobat SN74GTL2007 datasheet (영어)

SN74GTL2007

활성

데이터 시트

지금 주문

제품 상세 정보

Bits (#)

Data rate (max) (Mbps)

100

Topology

Open drain, Push-Pull

Direction control (typ)

Fixed-direction

Vin (min) (V)

Vin (max) (V)

3.6

Vout (min) (V)

0.8

Vout (max) (V)

3.6

Applications

MDIO, PMBus, SDIO, SMBus

Features

Overvoltage tolerant inputs

Technology family

GTL

Supply current (max) (mA)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Bits (#)

Data rate (max) (Mbps)

100

Topology

Open drain, Push-Pull

Direction control (typ)

Fixed-direction

Vin (min) (V)

Vin (max) (V)

3.6

Vout (min) (V)

0.8

Vout (max) (V)

3.6

Applications

MDIO, PMBus, SDIO, SMBus

Features

Overvoltage tolerant inputs

Technology family

GTL

Supply current (max) (mA)

Rating

Catalog

Operating temperature range (°C)

-40 to 85

TSSOP (PW)

62.08 mm² 9.7 x 6.4

Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
Series Termination on TTL Outputs of 30
Latch-Up Testing Done to JEDEC Standard JESD 78
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

Operates as a GTL-/GTL/GTL+ to LVTTL or LVTTL to GTL-/GTL/GTL+ Translator
Series Termination on TTL Outputs of 30
Latch-Up Testing Done to JEDEC Standard JESD 78
ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B, Class II)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The SN74GTL2007 is a 12-bit translator to interface between the 3.3-V LVTTL chip set I/O and the Xeon. processor GTL-/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor applications.

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16개 모두 보기

	유형	직함		날짜
*	Data sheet	SN74GTL2007 datasheet		2005/03/23
	Application note	Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators	PDF \| HTML	2024/07/12
	Application note	Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A)	PDF \| HTML	2024/07/03
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)		2021/07/26
	Selection guide	Voltage Translation Buying Guide (Rev. A)		2021/04/15
	Selection guide	Logic Guide (Rev. AB)		2017/06/12
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)		2015/12/02
	User guide	LOGIC Pocket Data Book (Rev. B)		2007/01/16
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection		2004/07/08
	Application note	TI IBIS File Creation, Validation, and Distribution Processes		2002/08/29
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices		2002/05/10
	User guide	GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A)		2001/09/15
	Selection guide	Advanced Bus Interface Logic Selection Guide		2001/01/09
	Application note	GTL/BTL: A Low-Swing Solution for High-Speed Digital Logic (Rev. A)		1997/03/01
	Application note	Understanding Advanced Bus-Interface Products Design Guide		1996/05/01
	Selection guide	Logic Guide (Rev. AC)	PDF \| HTML	1994/06/01