홈 전원 관리 선형 및 저손실(LDO) 레귤레이터
홈
전원 관리
선형 및 저손실(LDO) 레귤레이터

TPS754

활성

전원 양호 및 활성화를 지원하는 2A, 초저손실 전압 레귤레이터

지금 주문
데이터시트

이 제품의 최신 버전이 있습니다

open-in-new 대안 비교
다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능
TPS7A52 활성 2A, 낮은 VIN(1.1V), 저잡음, 고정밀, 초저손실(LDO) 전압 레귤레이터 Lower noise performance in smaller enhanced QFN package

TPS754

활성
데이터시트 지금 주문

제품 상세 정보

Output options Adjustable Output, Fixed Output Iout (max) (A) 2 Vin (max) (V) 5.5 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 3.3 Noise (µVrms) 60 Iq (typ) (mA) 0.07 Thermal resistance θJA (°C/W) 43 Rating Catalog Load capacitance (min) (µF) 47 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 PSRR at 100 KHz (dB) 15 Dropout voltage (Vdo) (typ) (mV) 210 Operating temperature range (°C) -40 to 125
Output options Adjustable Output, Fixed Output Iout (max) (A) 2 Vin (max) (V) 5.5 Vin (min) (V) 2.7 Vout (max) (V) 5.5 Vout (min) (V) 1.5 Fixed output options (V) 1.5, 1.8, 2.5, 3.3 Noise (µVrms) 60 Iq (typ) (mA) 0.07 Thermal resistance θJA (°C/W) 43 Rating Catalog Load capacitance (min) (µF) 47 Regulated outputs (#) 1 Features Enable, Power good Accuracy (%) 2 PSRR at 100 KHz (dB) 15 Dropout voltage (Vdo) (typ) (mV) 210 Operating temperature range (°C) -40 to 125
HTSSOP (PWP) 20 41.6 mm² 6.5 x 6.4
  • 2-A Low-Dropout Voltage Regulator
  • Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed Output and Adjustable Versions
  • Open Drain Power-On Reset With 100ms Delay (TPS752xxQ)
  • Open Drain Power-Good (PG) Status Output (TPS754xxQ)
  • Dropout Voltage Typically 210 mV at 2 A (TPS75233Q)
  • Ultralow 75-µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection
  • APPLICATIONS
    • Telecom
    • Servers
    • DSP, FPGA Supplies

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
  • 2-A Low-Dropout Voltage Regulator
  • Available in 1.5 V, 1.8 V, 2.5 V, 3.3 V Fixed Output and Adjustable Versions
  • Open Drain Power-On Reset With 100ms Delay (TPS752xxQ)
  • Open Drain Power-Good (PG) Status Output (TPS754xxQ)
  • Dropout Voltage Typically 210 mV at 2 A (TPS75233Q)
  • Ultralow 75-µA Typical Quiescent Current
  • Fast Transient Response
  • 2% Tolerance Over Specified Conditions for Fixed-Output Versions
  • 20-Pin TSSOP PowerPAD™ (PWP) Package
  • Thermal Shutdown Protection
  • APPLICATIONS
    • Telecom
    • Servers
    • DSP, FPGA Supplies

PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.

The TPS752xxQ and TPS754xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233Q, TPS75433Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when EN is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = +25°C.

The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage.

The TPS754xxQ has a power good terminal (PG) as an active high, open drain output for use with a power-on reset or a low-battery indicator.

The TPS754xxQ and TPS752xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS754xxQ and TPS752xxQ families are available in a 20-pin TSSOP (PWP) package.

The TPS752xxQ and TPS754xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 2 A of output current with a dropout of 210 mV (TPS75233Q, TPS75433Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically
210 mV at an output current of 2 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 2 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when EN is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ = +25°C.

The RESET (SVS, POR, or power on reset) output of the TPS752xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS752xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage.

The TPS754xxQ has a power good terminal (PG) as an active high, open drain output for use with a power-on reset or a low-battery indicator.

The TPS754xxQ and TPS752xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS754xxQ and TPS752xxQ families are available in a 20-pin TSSOP (PWP) package.
open-in-new 기타 선형 및 저손실(LDO) 레귤레이터 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기4
유형 직함 날짜
* Data sheet Fast-Transient-Response 2-A Low-Dropout Voltage Regulators datasheet (Rev. C) 2007/10/19
Application note LDO Noise Demystified (Rev. B) PDF | HTML 2020/08/18
Application note PowerPAD™ Thermally Enhanced Package (Rev. H) 2018/07/06
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 2017/08/09

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

레퍼런스 디자인

TIDA-00207 — EN55011 준수, 산업용 온도, 10/100Mbps 이더넷 PHY 브릭 레퍼런스 디자인

This Ethernet PHY Brick reference design enables Texas Instruments customers to quickly design systems and release them to market, using TI industrial Ethernet PHY transceiver devices, fully compliant to EN5501 Class A EMI requirements. A 50 Pin Interface has been provided to interface with 32-Bit (...)
Design guide: PDF
회로도: PDF
레퍼런스 디자인

TIDA-00928 — 파이버 또는 연선 인터페이스를 지원하는 EMI/EMC 준수 10/100Mbps 이더넷 브릭 레퍼런스 디자인

This ethernet brick reference design provides a simplified solution that eliminates the need to have multiple boards for copper or fiber interface. It uses a small form factor, low power 10/100 Mbps ethernet transceiver to reduce board size for a cost optimized and scalable solution with reduced (...)
Design guide: PDF
회로도: PDF
패키지 핀 다운로드
HTSSOP (PWP) 20 옵션 보기
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상