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LMK04828

ACTIVE

Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

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Data sheet

LMK04828

ACTIVE
Data sheet Order now

Product details

Number of input channels 3 Number of outputs 15 RMS jitter (fs) 88 Features JESD204B Output frequency (min) (MHz) 0.289 Output frequency (max) (MHz) 3080 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Operating temperature range (°C) -40 to 85
Number of input channels 3 Number of outputs 15 RMS jitter (fs) 88 Features JESD204B Output frequency (min) (MHz) 0.289 Output frequency (max) (MHz) 3080 Output type LVCMOS, LVDS, LVPECL Input type LVCMOS, LVDS, LVPECL Supply voltage (min) (V) 3.15 Supply voltage (max) (V) 3.45 Operating temperature range (°C) -40 to 85
WQFN (NKD) 64 81 mm² 9 x 9
  • JEDEC JESD204B Support
  • Ultra-Low RMS Jitter
    • 88 fs RMS Jitter (12 kHz to 20 MHz)
    • 91 fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks from PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.1 GHz
    • LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
  • Up to 1 Buffered VCXO/Crystal Output from PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switch-Over Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode When Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (even and odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25-ps Step Analog Delay
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40 to 85°C
  • Supports 105°C PCB Temperature (Measured at Thermal Pad)
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)
  • JEDEC JESD204B Support
  • Ultra-Low RMS Jitter
    • 88 fs RMS Jitter (12 kHz to 20 MHz)
    • 91 fs RMS Jitter (100 Hz to 20 MHz)
    • –162.5 dBc/Hz Noise Floor at 245.76 MHz
  • Up to 14 Differential Device Clocks from PLL2
    • Up to 7 SYSREF Clocks
    • Maximum Clock Output Frequency 3.1 GHz
    • LVPECL, LVDS, HSDS, LCPECL Programmable Outputs from PLL2
  • Up to 1 Buffered VCXO/Crystal Output from PLL1
    • LVPECL, LVDS, 2xLVCMOS Programmable
  • Dual Loop PLLatinum™ PLL Architecture
  • PLL1
    • Up to 3 Redundant Input Clocks
      • Automatic and Manual Switch-Over Modes
      • Hitless Switching and LOS
    • Integrated Low-Noise Crystal Oscillator Circuit
    • Holdover Mode When Input Clocks are Lost
  • PLL2
    • Normalized [1 Hz] PLL Noise Floor of
      –227 dBc/Hz
    • Phase Detector Rate up to 155 MHz
    • OSCin Frequency-Doubler
    • Two Integrated Low-Noise VCOs
  • 50% Duty Cycle Output Divides, 1 to 32
    (even and odd)
  • Precision Digital Delay, Dynamically Adjustable
  • 25-ps Step Analog Delay
  • Multi-Mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: –40 to 85°C
  • Supports 105°C PCB Temperature (Measured at Thermal Pad)
  • 3.15-V to 3.45-V Operation
  • Package: 64-Pin QFN (9.0 mm × 9.0 mm × 0.8 mm)

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.

The LMK0482x family is the industry’s highest performance clock conditioner with JEDEC JESD204B support.

The 14 clock outputs from PLL2 can be configured to drive seven JESD204B converters or other logic devices, using device and SYSREF clocks. SYSREF can be provided using both DC and AC coupling. Not limited to JESD204B applications, each of the 14 outputs can be individually configured as high-performance outputs for traditional clocking systems.

The high performance, combined with features such as the ability to trade off between power or performance, dual VCOs, dynamic digital delay, holdover, and glitchless analog delay, make the LMK0482x family ideal for providing flexible high-performance clocking trees.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs datasheet (Rev. AS) PDF | HTML 27 Sep 2017
Application note Powering Sensitive Noise ADC Designs with the TPS62913 Low-Noise Buck Converter PDF | HTML 30 Sep 2020
Application note Multi-Clock Synchronization 30 Dec 2019
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML 04 Jun 2019
User guide LMK04826/28 User’s Guide (Rev. B) 13 Mar 2018
Technical article Preparing for 5G applications: sync your multichannel JESD204B data acquisition sy PDF | HTML 28 Aug 2017
Technical article High-speed data converter clocking for JESD204B PDF | HTML 07 Jul 2017
Technical article How to complete your RF sampling solution PDF | HTML 18 May 2016
Technical article Timing is Everything: Design JESD204B clocking using system reference modes PDF | HTML 16 Jun 2015
Analog Design Journal Analog Applications Journal 2Q 2015 28 Apr 2015
Analog Design Journal JESD204B multi-device synchronization: Breaking down the requirements 28 Apr 2015
Analog Design Journal When is the JESD204B interface the right choice? 22 Jan 2014
User guide HSDC-SEK-10 17 Jan 2013
Application note LMK04828 as a Clock Source for the ADS42JB69 14 Nov 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK04828BEVM — LMK04828 evaluation module

The LMK04828BEVM and LMK04826BEVM evaluation modules (EVMs) support the LMK0482x family of devices. The the LMK0482x devices are the industry's highest performance clock conditioners with JEDEC JESD204B support. The dual-loop architecture of the PLLATINUM™ integrated (...)

User guide: PDF
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Support software

CLOCKDESIGNTOOL — Clock Design Tool Software

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

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Support software

TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices

Texas Instruments clocks and synthesizers (TICS) pro software is used to program the evaluation modules (EVMs) for product numbers with these prefixes: CDC, LMK and LMX. These products include phase-locked loops and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.

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Simulation model

LMK04828 IBIS Model (Rev. F)

SNAM148F.ZIP (175 KB) - IBIS Model
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Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Design tool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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