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EVALUATION BOARD Download 499
APPLICATION SOFTWARE & FRAMEWORK Download
The LMK04821EVM supports the LMK0482x family of products, the industry's highest performance clock conditioners with JEDEC JESD204B support. The dual loop PLLatinum™ architecture enables sub-100 fs jitter (12 kHz to 20 MHz) using a low noise VCXO module. The dual loop architecture consists of (...)
- JEDEC JESD204B support to generate pulsed SYSREF.
- Evaluation board configurable using CodeLoader software.
- Accepts differential or single-ended/LVCMOS input clock
- LVPECL outputs can be connected with balun to test equipment or single-ended by using 50-ohm termination on unconnected output.
Texas Instruments Clocks and Synthesizers (TICS) Pro Software
TICSPRO-SW — The TICS Pro software is used to program the evaluation modules (EVMs) for device numbers with these prefixes: CDC, LMK and LMX. These devices include PLLs and voltage-controlled oscillators (PLL+VCO), synthesizers and clocking devices.
IDE, CONFIGURATION, COMPILER OR DEBUGGER Download
- Program EVMs through the USB2ANY Interface Adaptor or onboard USB interface.
- Export programming configurations for use in end application.
CodeLoader Software for device register programming CODELOADER — The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
SUPPORT SOFTWARE Download
SNAC072AK.ZIP (62249 KB) SIMULATION MODEL Download
SNAM167.IBS (648 KB) - IBIS Model SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
DESIGN TOOL Download
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
Clock tree architect programming software
CLOCK-TREE-ARCHITECT — Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
- Accepts customer specific design requirements such as input frequencies, output frequencies, clock formats and clock counts
- Generates clock trees by taking into account a variety of advanced specifications, such as noise floor and phase determinism requirements
- Presents clear and intuitive block (...)