LMK04828 evaluation module


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The LMK04828BEVM and LMK04826BEVM evaluation modules (EVMs) support the LMK0482x family of devices. The the LMK0482x devices are the industry's highest performance clock conditioners with JEDEC JESD204B support. The dual-loop architecture of the PLLATINUM™ integrated circuits enables sub-100 fs jitter (12 kHz to 20 MHz) using a low-noise VCXO module. The dual-loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage controlled oscillator (VCO).

The first PLL (PLL1) provides a low-noise jitter cleaner function. The second PLL (PLL2) performs the clock and SYSREF generation. PLL1 can be configured to either work with an external VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO.

The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.

  • JEDEC JESD204B support
  • Ultra-low rms jitter performance
  • Dual-loop architecture
  • 3 redundant input clocks with LOS
  • Precision digital delay, fixed or dynamically adjustable
Clock jitter cleaners & synchronizers
LMK04828 Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

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Evaluation board

LMK04828BEVM – LMK04828/26 Evaluation Module

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Technical documentation

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Type Title Date
* User guide LMK04826/28 User’s Guide (Rev. B) Mar. 13, 2018
Certificate LMK04828BEVM EU Declaration of Conformity (DoC) Jan. 02, 2019
Data sheet LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs datasheet (Rev. AS) Sep. 27, 2017

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