74ACT16861
- Members of the Texas Instruments WidebusTM Family
- Inputs Are TTL-Voltage Compatible
- 3-State Outputs Drive Bus Lines Directly
- Flow-Through Architecture Optimizes PCB Layout
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- EPICTM (Enhanced-Performance Implanted CMOS) 1-
m Process - 500-mA Typical Latch-Up Immunity at 125°C
- Package Options Include Shrink Plastic Small-Outline 300-mil (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
The 'ACT16861 are noninverting 20-bit transceivers designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
The 'ACT16861 can be used as two 10-bit transceivers or one 20-bit
transceiver. They allow data transmission from the A bus to the B bus
or from the B bus to the A bus, depending upon the logic level at the
output-enable (
or 
) inputs. The output-enable inputs
can be used to disable the device so that the buses are effectively
isolated.
The 74ACT16861 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16861 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16861 is characterized for operation from -40°C to 85°C.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 20-Bit Bus Transceivers With 3-State Outputs datasheet (Rev. B) | 1996年 11月 1日 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021年 7月 26日 | ||
| Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
| Application note | Selecting the Right Level Translation Solution (Rev. A) | 2004年 6月 22日 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
| Application note | CMOS Power Consumption and CPD Calculation (Rev. B) | 1997年 6月 1日 | ||
| Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
| Application note | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 1996年 4月 1日 |
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