產品詳細資料

Sample rate (max) (Msps) 1500 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.35 Power consumption (typ) (mW) 4000 Architecture Pipeline SNR (dB) 63 ENOB (Bits) 9.9 SFDR (dB) 70 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1500 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 3200 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 1.35 Power consumption (typ) (mW) 4000 Architecture Pipeline SNR (dB) 63 ENOB (Bits) 9.9 SFDR (dB) 70 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² (10 mm × 10 mm)
  • 14-Bit, Dual-Channel, 1.5-GSPS ADC
  • Noise Floor: –151.8 dBFS/Hz
  • RF Input Supports Up to 4 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 950 MHz, –2 dBFS):
    • SNR: 61.1 dBFS
    • SFDR: 67-dBc HD2, HD3
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 64-dBc HD2, HD3
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel Up to 12.5 Gbps
  • Power Dissipation: 2 W/Ch at 1.5 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)
  • 14-Bit, Dual-Channel, 1.5-GSPS ADC
  • Noise Floor: –151.8 dBFS/Hz
  • RF Input Supports Up to 4 GHz
  • Aperture Jitter: 90 fS
  • Channel Isolation: 95 dB at fIN = 1.8 GHz
  • Spectral Performance (fIN = 950 MHz, –2 dBFS):
    • SNR: 61.1 dBFS
    • SFDR: 67-dBc HD2, HD3
  • Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
    • SNR: 58.9 dBFS
    • SFDR: 64-dBc HD2, HD3
  • On-Chip Digital Down-Converters:
    • Up to 4 DDCs (Dual-Band Mode)
    • Up to 3 Independent NCOs per DDC
  • On-Chip Input Clamp for Overvoltage Protection
  • Programmable On-Chip Power Detectors With Alarm Pins for AGC Support
  • On-Chip Dither
  • On-Chip Input Termination
  • Input Full-Scale: 1.35 VPP
  • Support for Multi-Chip Synchronization
  • JESD204B Interface:
    • Subclass 1-Based Deterministic Latency
    • 4 Lanes Per Channel Up to 12.5 Gbps
  • Power Dissipation: 2 W/Ch at 1.5 GSPS
  • 72-Pin VQFN Package (10 mm × 10 mm)

The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



The ADC32RF42 device is a 14-bit, 1.5-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF42 delivers a noise spectral density of –151.8 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.

Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.

The ADC32RF42 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).



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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 ADC32RF42 Dual-Channel, 14-Bit, 1.5-GSPS, Analog-to-Digital Converter datasheet PDF | HTML 2017/5/16
應用說明 Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) 2017/9/5

設計與開發

如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

ADC32RF42EVM — ADC32RF42 雙通道 14 位元 1.5 GSPS 射頻取樣 ADC 評估模組

ADC32RF42 評估模組 (EVM) 展示了具有 JESD204B 介面的雙 1.5-GSPS 14 位元類比轉數位轉換器 (ADC) 的性能。此 EVM 包含 ADC32RF42 裝置,而且 LMK04828 與TI 電壓穩壓器會提供 JESD204B 時鐘計時功能,以提供必要的電壓。

ADC 各通道的輸入預設連接至變壓器輸入電路,可連接至 50Ω 單端訊號來源。時鐘參考輸入可透過變壓器輸入提供,並可連接至 50Ω 單端時鐘來源。板載 LMK04828 可用於產生必要的 JESD204B 時鐘。透過板載 USB 連線和 Windows® 版 GUI 提供配置暫存器的存取。FMC (...)

使用指南: PDF
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韌體

TI204C-IP — Request for JESD204 rapid design IP

JESD204 快速設計 IP 被設計用於幫助 FPGA 工程師快速實現可運作的 JESD204 系統,從而加速開發過程。該 IP 的架構設計使得下游數位處理和其他應用邏輯能夠隔離於 JESD204 通訊協定的大多數性能和時序關鍵約束之外。該 IP 能夠幫助設計人員減少韌體開發時間並簡化 FPGA 的整合。

JESD204 快速設計 IP 無需權利金,用於 TI 高速資料轉換器。TI 將協助使用者配置初始連結,針對特定 FPGA 平台與 TI 資料轉換器 JMODE 之間的使用進行自訂。TI 將在 IP 測試完成並準備部署後,透過安全下載連結提供 IP。

JESD204 快速設計 IP 支援下列 (...)

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開發模組 (EVM) 的 GUI

SBAC148 — ADC32RFxxEVM SPI GUI Installer

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模擬型號

ADC32RF45 IBIS Model

SBAM273.ZIP (46 KB) - IBIS 模型
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模擬型號

ADC32RF45 IBIS-AMI Model

SBAM274.ZIP (3109 KB) - IBIS-AMI 模型
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計算工具

FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator

這個 Excel 計算機為系統設計人員提供了一種簡化直接 RF 取樣接收器設計和偵錯的方法。它提供了三項功能:頻率規劃、類比濾波和降頻濾波器雜散定位

在概念階段,頻率規劃工具能夠精確調整 ADC 取樣率和輸入頻率位置,以在阻塞事件期間最佳化無雜散動態範圍 (SFDR)。某些設計在這兩方面都具有靈活性;而其他一些設計,例如 L 波段接收器或無線基礎設施基地台,則處理固定頻帶,僅提供取樣率調整功能。

外部 RF 濾波器回應高度依賴於系統 SFDR 目標與 ADC 本身的 SFDR 性能;類比濾波器工具可在設計階段提供協助。

在系統啟動期間出現快速傅立葉轉換 (FFT) (...)

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
VQFNP (RMP) 72 Ultra Librarian

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