The ADC34J4x is a high-linearity, ultra-low power, quad-channel, 14-bit, 50-MSPS to 160-MSPS, analog-to-digital converter (ADC). The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The ADC34J4x family supports serial current-mode logic (CML) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 14-bit data from each channel. The ADC34J4x devices support subclass 1 with interface speeds up to 3.2 Gbps.
| 重要文件 | 類型 | 標題 | 格式選項 | 日期 |
|---|---|---|---|---|
| * | Data sheet | ADC34J4x Quad-Channel, 14-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with a JESD204B Interface datasheet (Rev. B) | PDF | HTML | 2014年 11月 10日 |
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ADC34J44 EVM 展示了低功耗四路 125Msps 14 位元 ADC 的性能。其中包括 ADC34J44 裝置、LMK04828 JESD204B 計時解決方案及 TI 電壓穩壓器，以提供必要的電壓。ADC 的輸入連接至變壓器輸入，可連接至 50 ohm 單端訊號來源。時鐘參考輸入可透過變壓器輸入提供，並可連接至 50 ohm 單端時鐘來源。板載 LMK04828 可用於產生必要的 JESD204B 時鐘。透過板載 USB 接頭和 GUI 提供暫存器存取權。對於完整的評估系統，TI 還提供 TSW14J50 資料擷取卡和高速資料轉換器專業級軟體。
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。