ADS1287
- Selectable Operating Modes
- High-Resolution Mode:
- SNR: 113 dB (1000 SPS, Gain = 1)
- Power: 4.5 mW
- Low-Power Mode:
- SNR: 110 dB (1000 SPS, Gain = 1)
- Power: 2.4 mW
- THD: –115 dB
- CMRR: 115 dB
- High-Impedance CMOS PGA
- Gains 1, 2, 4, 8, and 16
- Data Rates: 62.5 SPS to 1000 SPS
- Flexible Digital
Filter:
- Sinc + FIR + IIR (Selectable)
- Linear and Minimum Phase Response
- Programmable High-Pass Filter
- Offset and Gain Calibration
- Synchronization Control
- SPI-Compatible Interface
- Analog Power Supply: 5 V or ±2.5 V
- Digital Power Supply: 2.5 V to 3.3 V
The ADS1287 device is a low-power, analog-to-digital converter (ADC), with an integrated programmable gain amplifier (PGA) and finite-impulse-response (FIR) digital filter. The ADC is suitable for the demanding needs of seismic equipment requiring precision digitizing with low power consumption.
The ADC features a programmable-gain, high-impedance complementary metal oxide semiconductor (CMOS) amplifier, suitable for direct connection of geophone and hydrophone sensors to the ADC over a wide range of input signals (±2.5 V to ±0.156 V).
The ADC incorporates a fourth-order, inherently stable, delta-sigma (ΔΣ) modulator. The modulator digital output is filtered and decimated by the internal FIR digital filter to yield the ADC conversion result.
The FIR digital filter provides data rates up to 1000 samples per second (SPS). The high-pass filter (HPF) removes DC and low frequency components from the conversion result. On-chip gain and offset scaling registers support system calibration.
Together, the amplifier, modulator, and digital filter dissipate 4.5 mW in high-resolution mode (2.4 mW in low-power mode). The ADC is packaged in a compact 5-mm × 4-mm VQFN package. The ADC is fully specified over the –40°C to +85°C temperature range.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADS1287 Low-Power, 1000-SPS, Wide-Bandwidth, Analog-to-Digital Converter With Programmable Gain Amplifier datasheet (Rev. B) | PDF | HTML | 2019/8/27 | ||
| 應用說明 | Calculating Conversion Latency and System Cycle Time for Delta-Sigma ADCs (Rev. A) | PDF | HTML | 2024/3/18 | |||
| 應用說明 | QFN and SON PCB Attachment (Rev. C) | PDF | HTML | 2023/12/6 | |||
| 應用說明 | Digital Filter Types in Delta-Sigma ADCs (Rev. A) | PDF | HTML | 2023/3/29 | |||
| 電子書 | Fundamentals of Precision ADC Noise Analysis (Rev. A) | 2020/6/19 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
類比工程師的計算機旨在加速類比電路設計工程師定期使用的許多重複計算。此基於 PC 的工具提供圖形介面，列出各種常見計算，從使用回饋電阻器設定運算放大器增益到選擇適當的電路設計元件以穩定類比數位轉換器 (ADC) 驅動緩衝電路。
除了作為獨立工具使用外，此計算機還與類比工程師口袋參考中描述的概念相得益彰。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RHF) | 24 | Ultra Librarian |