ADS1287
- Selectable Operating Modes
- High-Resolution Mode:
- SNR: 113 dB (1000 SPS, Gain = 1)
- Power: 4.5 mW
- Low-Power Mode:
- SNR: 110 dB (1000 SPS, Gain = 1)
- Power: 2.4 mW
- THD: –115 dB
- CMRR: 115 dB
- High-Impedance CMOS PGA
- Gains 1, 2, 4, 8, and 16
- Data Rates: 62.5 SPS to 1000 SPS
- Flexible Digital Filter:
- Sinc + FIR + IIR (Selectable)
- Linear and Minimum Phase Response
- Programmable High-Pass Filter
- Offset and Gain Calibration
- Synchronization Control
- SPI-Compatible Interface
- Analog Power Supply: 5 V or ±2.5 V
- Digital Power Supply: 2.5 V to 3.3 V
The ADS1287 device is a low-power, analog-to-digital converter (ADC), with an integrated programmable gain amplifier (PGA) and finite-impulse-response (FIR) digital filter. The ADC is suitable for the demanding needs of seismic equipment requiring precision digitizing with low power consumption.
The ADC features a programmable-gain, high-impedance complementary metal oxide semiconductor (CMOS) amplifier, suitable for direct connection of geophone and hydrophone sensors to the ADC over a wide range of input signals (±2.5 V to ±0.156 V).
The ADC incorporates a fourth-order, inherently stable, delta-sigma (ΔΣ) modulator. The modulator digital output is filtered and decimated by the internal FIR digital filter to yield the ADC conversion result.
The FIR digital filter provides data rates up to 1000 samples per second (SPS). The high-pass filter (HPF) removes DC and low frequency components from the conversion result. On-chip gain and offset scaling registers support system calibration.
Together, the amplifier, modulator, and digital filter dissipate 4.5 mW in high-resolution mode (2.4 mW in low-power mode). The ADC is packaged in a compact 5-mm × 4-mm VQFN package. The ADC is fully specified over the –40°C to +85°C temperature range.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | ADS1287 Low-Power, 1000-SPS, Wide-Bandwidth, Analog-to-Digital Converter With Programmable Gain Amplifier datasheet (Rev. B) | PDF | HTML | 2019年 8月 27日 |
Application note | Calculating Conversion Latency and System Cycle Time for Delta-Sigma ADCs (Rev. A) | PDF | HTML | 2024年 3月 18日 | |
Application note | QFN and SON PCB Attachment (Rev. C) | PDF | HTML | 2023年 12月 6日 | |
Application note | Digital Filter Types in Delta-Sigma ADCs (Rev. A) | PDF | HTML | 2023年 3月 29日 | |
E-book | Fundamentals of Precision ADC Noise Analysis | 2020年 6月 19日 |
設計與開發
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ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
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精密度運算放大器 (Vos<1mV)
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TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VQFN (RHF) | 24 | Ultra Librarian |
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