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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS42JB46

現行

雙通道、14 位元、160-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

ADS42JB46

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 160 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2.5 Power consumption (typ) (mW) 1360 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12 SFDR (dB) 100 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 160 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2.5 Power consumption (typ) (mW) 1360 Architecture Pipeline SNR (dB) 75.2 ENOB (Bits) 12 SFDR (dB) 100 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RGC) 64 81 mm² 9 x 9
  • Dual-Channel ADCs
  • 14-Bit Resolution
  • Maximum Clock Rate: 160 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two- and Four-Lane Support
  • Analog Input Buffer with High-Impedance
    Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm QFN-64
  • Power Dissipation: 679 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 72.9 dBFS
      • SFDR: 90 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.2 dBFS
      • SFDR: 84 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3
  • Dual-Channel ADCs
  • 14-Bit Resolution
  • Maximum Clock Rate: 160 MSPS
  • JESD204B Serial Interface
    • Subclass 0, 1, 2 Compliant
    • Up to 3.125 Gbps
    • Two- and Four-Lane Support
  • Analog Input Buffer with High-Impedance
    Input
  • Flexible Input Clock Buffer:
    Divide-by-1, -2, and -4
  • Differential Full-Scale Input: 2 VPP and 2.5 VPP
    (Register Programmable)
  • Package: 9-mm × 9-mm QFN-64
  • Power Dissipation: 679 mW/Ch
  • Aperture Jitter: 85 fS rms
  • Internal Dither
  • Channel Isolation: 100 dB
  • Performance:
    • fIN = 170 MHz at 2 VPP, –1 dBFS
      • SNR: 72.9 dBFS
      • SFDR: 90 dBc for HD2, HD3
      • SFDR: 100 dBc for Non HD2, HD3
    • fIN = 170 MHz at 2.5 VPP, –1 dBFS
      • SNR: 74.2 dBFS
      • SFDR: 84 dBc for HD2, HD3 and
        95 dBc for Non HD2, HD3

The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.

The ADS42JB46 is a high-linearity, dual-channel, 14-bit, 160-MSPS, analog-to-digital converter (ADC). This device supports the JESD204B serial interface with data rates up to 3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy, thus making driving analog inputs up to very high input frequencies easy. A sampling clock divider allows more flexibility for system clock architecture design. The device employs internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.
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重要文件 類型 標題 格式選項 日期
* Data sheet ADS42JB46 Dual-Channel, 14-Bit, 160-MSPS Analog-to-Digital Converter datasheet (Rev. B) PDF | HTML 2015年 9月 2日
Application note Correcting the Low-Frequency Response of the ADS42LBxx, ADS42JBxx for Time-Domai 2016年 5月 2日
User guide TSW14J56 JESD204B High-Speed Data Capture/ Pattern Generator Card User's Guide (Rev. C) PDF | HTML 2016年 1月 11日
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 2015年 3月 19日
User guide Interoperability of TI ADS42JB69 Family of JESD204B ADCs with Altera FPGAs 2013年 10月 4日

設計與開發

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開發板

ADS42JB46EVM — ADS42JB46 雙通道、14 位元、160 MSPS 類比轉數位轉換器評估模組

The ADS42JB46EVM is an evaluation module (EVM) that allows for the evaluation of the ADS42JB46 and LMK04828 clock jitter cleaner. ADS42JB46 is a low-power, 14-bit, 160-MSPS analog-to-digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. The EVM has (...)

使用指南: PDF
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TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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開發模組 (EVM) 的 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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SLAC544 — ADS42JBxx GUI v1p1 installer

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模擬型號

ADS42JB46 IBIS Model

SBAM174.ZIP (174 KB) - IBIS Model
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
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