首頁 邏輯和電壓轉換 緩衝器、驅動器和收發器 通用收發器
首頁
邏輯和電壓轉換
緩衝器、驅動器和收發器
通用收發器

CD74AC652

現行

具有 3 態輸出的八路非反相匯流排收發器/暫存器

立即訂購
產品規格表

CD74AC652

現行
產品規格表 立即訂購

產品詳細資料

Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family AC Rating Catalog Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 1.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 24 IOH (max) (mA) -24 Input type CMOS Output type CMOS Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Technology family AC Rating Catalog Operating temperature range (°C) -55 to 125
SOIC (DW) 24 159.65 mm² 15.5 x 10.3
  • Buffered inputs
  • Typical propagation delay:
    • 5.3 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST*/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    • Fanout of 15 FAST* ICs
    • Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

* FAST is a Registered Trademark of Fairchild Semiconductor Corp.
  • Buffered inputs
  • Typical propagation delay:
    • 5.3 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST*/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    • Fanout of 15 FAST* ICs
    • Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

* FAST is a Registered Trademark of Fairchild Semiconductor Corp.

The RCA CD54/74AC651 and CD54/74AC652 and the CD54/74ACT651 and CD54/74ACT652 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC651 and CD54/74ACT651 have inverting outputs. The CD54/74AC562 and CD54/74ACT652 have non-inverting outputs. These devices consist of bus tranceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output Enables OEAB and OE\BA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data, and a HIGH selects stored data. The following examples demonstrate the four fundamental bus-management functions that can be performed with the octal-bus transceivers and registers.

Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OE\BA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are a high impedance, each set of bus lines will remain at its last state.

The CD74AC/ACT651 and CD74AC/ACT652 are supplied in 24-lead dual-in-line narrow-body plastic packages (EN suffix) and in 24-lead dual-in-line small-outline plastic packages (M suffix). Both package ty0es are operable over the following temperature ranges. Commerical (0 to 70°C); industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54AC/ACT651 and CD54AC/ACT652, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.

The RCA CD54/74AC651 and CD54/74AC652 and the CD54/74ACT651 and CD54/74ACT652 3-state, octal-bus transceiver/registers use the RCA ADVANCED CMOS technology. The CD54/74AC651 and CD54/74ACT651 have inverting outputs. The CD54/74AC562 and CD54/74ACT652 have non-inverting outputs. These devices consist of bus tranceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output Enables OEAB and OE\BA are provided to control the transceiver functions. SAB and SBA control pins are provided to select whether real-time or stored data is transferred. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A LOW input level selects real-time data, and a HIGH selects stored data. The following examples demonstrate the four fundamental bus-management functions that can be performed with the octal-bus transceivers and registers.

Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the appropriate clock pins (CAB or CBA) regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OE\BA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are a high impedance, each set of bus lines will remain at its last state.

The CD74AC/ACT651 and CD74AC/ACT652 are supplied in 24-lead dual-in-line narrow-body plastic packages (EN suffix) and in 24-lead dual-in-line small-outline plastic packages (M suffix). Both package ty0es are operable over the following temperature ranges. Commerical (0 to 70°C); industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54AC/ACT651 and CD54AC/ACT652, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.
open-in-new 尋找其它 通用收發器
下載 觀看有字幕稿的影片 影片

您可能會感興趣的類似產品

open-in-new 比較替代產品
引腳對引腳的功能與所比較的產品相同
SN74HCS245 現行 具有三態輸出的施密特觸發器輸入八路匯流排收發器 Longer average propagation delay (12ns), lower average drive strength (7.8mA)

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 13
類型 標題 日期
* Data sheet Octal-Bus Transceiver/Registers, 3-State datasheet 1998年 12月 3日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
More literature HiRel Unitrode Power Management Brochure 2009年 7月 7日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
TI.com 無法提供
封裝 引腳 下載
SOIC (DW) 24 檢視選項
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 資格摘要
  • 進行中可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片