CDC351

現行

具 3 態輸出的 1 線路至 10 線路 3.3-V 時鐘驅動器

立即訂購

產品規格表

document-pdfAcrobat 1-Line To 10-Line Clock Driver With 3-State Outputs datasheet (Rev. D) (英文)

CDC351

現行

產品規格表

立即訂購

產品詳細資料

Function

Single-ended

Output frequency (max) (MHz)

100

Number of outputs

10

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

0.6

Features

Pin control

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVTTL

Input type

LVTTL

Function

Single-ended

Output frequency (max) (MHz)

100

Number of outputs

10

Output supply voltage (V)

3.3

Core supply voltage (V)

3.3

Output skew (ps)

0.6

Features

Pin control

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVTTL

Input type

LVTTL

SOIC (DW)

24

159.65 mm² 15.5 x 10.3

SSOP (DB)

24

63.96 mm² 8.2 x 7.8

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
LVTTL-Compatible Inputs and Outputs
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Distributes One Clock Input to Ten Outputs
Distributed V_CC and Ground Pins Reduce Switching Noise
High-Drive Outputs (-32-mA I_OH, 32-mA I_OL)
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages

EPIC-IIB is a trademark of Texas Instruments Incorporated.

Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications
Operates at 3.3-V V_CC
LVTTL-Compatible Inputs and Outputs
Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V_CC)
Distributes One Clock Input to Ten Outputs
Distributed V_CC and Ground Pins Reduce Switching Noise
High-Drive Outputs (-32-mA I_OH, 32-mA I_OL)
State-of-the-Art EPIC-IIB^TM BiCMOS Design Significantly Reduces Power Dissipation
Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages

EPIC-IIB is a trademark of Texas Instruments Incorporated.

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V V_CC.

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V V_CC.

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.

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	類型	標題		日期
*	Data sheet	1-Line To 10-Line Clock Driver With 3-State Outputs datasheet (Rev. D)		2003年 6月 17日

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模擬型號

CDC351 IBIS Model

SCAC012.ZIP (7 KB) - IBIS Model

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SOIC (DW)	24	Ultra Librarian
SSOP (DB)	24	Ultra Librarian

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CDC351

具 3 態輸出的 1 線路至 10 線路 3.3-V 時鐘驅動器

CDC351

產品詳細資料

技術文件

設計與開發

CDC351 IBIS Model

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

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