CDCE949-Q1
- Qualified for Automotive Applications
- Member of Programmable Clock Generator Family
- CDCE913/CDCEL913: 1 PLLs, 3 Outputs
- CDCE925/CDCEL925: 2 PLLs, 5 Outputs
- CDCE937/CDCEL937: 3 PLLs, 7 Outputs
- CDCE949: 4 PLLs, 9 Outputs
- In-System Programmability and EEPROM
- Serial Programmable Volatile Register
- Non-Volatile EEPROM to Store Customer Settings
- Highly Flexible Clock Driver
- Three User-Definable Control Inputs [S0/S1/S2]; such as SSC-Selection, Frequency Switching, Output Enable or Power Down
- Generates Highly-Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Generates Common Clock Frequencies Used with TI DaVinci™, OMAP™, DSPs
- BlueTooth™, WLAN, Ethernet and GPS
- Programmable SSC Modulation
- Enables 0ppm Clock Generation
- Selectable Output Frequency up to 230MHz
- Flexible Input Clocking Concept
- External Crystal: 8MHz to 32MHz
- On-Chip VCXO: Pull-Range ±150ppm
- Single-Ended LVCMOS up to 160MHz
- Low-Noise PLL Core
- Integrated PLL Loop Filter Components
- Very Low Period Jitter (typical 60ps)
- Separate Output Supply Pins
- 3.3V and 2.5V
- 1.8V Device Power Supply
- Latch-Up Performance Meets 100mAPer JESD 78, Class I
- Wide Temperature Range –40°C to 125°C
- Packaged in TSSOP
- Development and Programming Kit for Ease PLL Design and Programming (TI ClockPro)
The CDCE949-Q1 is a modular PLL-based low-cost high-performance programmable clock synthesizer, multiplier, and divider. The device generates up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.
The CDCE949-Q1 has separate output supply pins, VDDOUT, of 2.5V to 3.3V.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.
The deep M/N divider ratio allows the generation of zero-ppm audio/video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.
All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This technique is common for reducing electro-magnetic interference (EMI).
Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.
The device supports non-volatile EEPROM programming for easy customization to the application. The CDCE949-Q1 is preset to a factory-default configuration (see the Default Device Configuration section). The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA/SCL bus, a 2-wire serial interface.
Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.
The CDCE949-Q1 operates in a 1.8V environment. The device operates within a temperature range of –40°C to 125°C.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCE949-Q1: Programmable 4-PLL VCXO Clock Synthesizer With 1.8V, 2.5V, and 3.3V LVCMOS Outputs datasheet (Rev. A) | PDF | HTML | 2025年 5月 30日 |
| Application note | Crystal or Crystal Oscillator Replacement with Silicon Devices | 2014年 6月 18日 | ||
| Application note | VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) | 2012年 4月 23日 | ||
| Application note | General I2C / EEPROM usage for the CDCE(L)9xx family | 2010年 1月 26日 | ||
| Application note | Troubleshooting I2C Bus Protocol | 2009年 10月 19日 | ||
| Application note | Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 | 2009年 9月 23日 | ||
| Application note | Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency | 2008年 3月 31日 |
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