CDCV304
- General-Purpose and PCI-X 1:4 Clock Buffer
- Operating Frequency
- 0 MHz to 200 MHz General-Purpose
- Low Output Skew: <100 ps
- Distributes One Clock Input to One Bank of Four Outputs
- Output Enable Control that Drives Outputs Low when OE is Low
- Operates from Single 3.3-V Supply or 2.5-V Supply
- PCI-X Compliant
- 8-Pin TSSOP Package
The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications.
The CDCV304 is characterized for operation from –40°C to 85°C for automotive and industrial applications.
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 3 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | CDCV304 200-MHz General-Purpose Clock Buffer, PCI-X Compliant datasheet (Rev. I) | PDF | HTML | 2017年 10月 16日 |
| Application note | Clocking Design Guidelines: Unused Pins | 2015年 11月 19日 | ||
| Application note | Using TI's CDCV304 w/Backplane Transceiver (TLK1201/1501/2201/2501/2701/3101) (Rev. A) | 2006年 4月 20日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
ADC08200EVM — 具有內部取樣保持功能的 ADC08200 8 位元 200 MSPS 低功耗 ADC 評估模組
ADC08200 評估模組 (EVM) 旨在評估高速
CMOS 介面 ADC08200。ADC08200EVM 提供簡單且最少的外部零組件，將系統成本和耗電量降到最低。
使用指南: PDF
設計工具
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
TIDA-00076 — 相鄰通道功率比 (ACPR) 和誤差向量幅度 (%EVM) 量測
This reference design discusses the use of the TSW3085EVM with the TSW3100 pattern generator to test adjacent channel power ratio (ACPR) and error vector magnitude (EVM) measurements of LTE baseband signals. By using the TSW3100 LTE GUI, patterns are loaded into the TSW3085EVM which is comprised of (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 8 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。