CDCVF2310-EP
- High-Performance 1:10 Clock Driver
- Operates up to 200 MHz at VDD 3.3 V
- Pin-to-Pin Skew < 100 ps at VDD 3.3 V
- VDD Range: 2.3 V to 3.6 V
- Output Enable Glitch Suppression
- Distributes One Clock Input to Two Banks of Five Outputs
- 25-Ω On-Chip Series Damping Resistors
- Packaged in 24-Pin TSSOP
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins (1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a 2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable sequence to distribute full period clock signals.
The CDCVF2310 is characterized for operation from –55°C to 125°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | CDCVF2310-EP 2.5-V to 3.3-V High Performance Clock Buffer datasheet | 2012/12/28 | |||
| * | 輻射及可靠性報告 | CDCVF2310MPWEP Relability Report | 2016/2/9 | |||
| * | 輻射及可靠性報告 | CDCVF2310MPWREP Reliability Report | 2016/2/9 | |||
| * | VID | CDCVF2310-EP VID V6213603 | 2016/6/21 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TSSOP (PW) | 24 | Ultra Librarian |
訂購與品質
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