DAC3174
- Dual-Channel
- 14-Bit Resolution
- Maximum Sample Rate: 500 MSPS
- Pin Compatible With Dual-Channel DAC3154, DAC3164, and Single-Channel DAC3151, DAC3161, and DAC3171
- Input Interface:
- 14 LVDS Inputs
- Single, 14-Bit Interface or Dual, 7-Bit Interface
- Single or Dual DDR Data Clock
- Internal FIFO
- Chip-to-Chip Synchronization
- Power Dissipation: 460 mW
- Spectral Performance at 20 MHz IF:
- SNR: 76 dBFS
- SFDR: 78 dBc
- Current-Sourcing DACs
- Compliance Range: –0.5 V to +1 V
- Package: 64-Pin VQFN (9 mm × 9 mm)
The DAC3174 is a dual-channel, 14-bit, 500-MSPS, digital-to-analog converter (DAC). The DAC3174 uses a 14-bit, low-voltage differential signaling (LVDS) digital bus, with one or two independent dual-data rate (DDR) data clocks for flexibility in providing data from different sources in each channel.
An input first-in first out block (FIFO) allows independent data and sample clocks. FIFO input and output pointers can be synchronized across multiple devices for precise signal synchronization.
The DAC outputs are current sourcing and terminate to GND with a compliance range of –0.5 V to +1 V.
The DAC3174 is pin compatible with the dual-channel, 500-MSPS, 12-bit DAC3164 and 10-bit DAC3154, and the single-channel, 500-MSPS, 14-bit DAC3171, 12-bit DAC3161, and 10-bit DAC3151.
The device is available in a 64-pin VQFN PowerPAD™ package. and is specified over the full industrial temperature range of –40°C to +85°C.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | DAC3174 Dual, 14-Bit, 500-MSPS, Digital-to-Analog Converter datasheet (Rev. B) | PDF | HTML | 2017/1/25 | ||
| 應用說明 | DAC348x Device Configuration and Synchronization | 2013/2/18 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。