JFE150
- Ultra-low noise:
- Voltage noise:
- 0.8 nV/√ Hz at 1 kHz, I DS = 5 mA
- 0.9 nV/√ Hz at 1 kHz, I DS = 2 mA
- Current noise: 1.8 fA/√ Hz at 1 kHz
- Voltage noise:
- Low gate current: 10 pA (max)
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Low input capacitance: 24 pF at V DS = 5 V
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High gate-to-drain and gate-to-source breakdown voltage: –40 V
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High transconductance: 68 mS
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Packages: Small SC70 and SOT-23
The JFE150 is a Burr-Brown™ discrete JFET built using Texas Instruments’ modern, high-performance, analog bipolar process. The JFE150 features performance not previously available in older discrete JFET technologies. The JFE150 offers the maximum possible noise-to-power efficiency and flexibility, where the quiescent current can be set by the user and yields excellent noise performance for currents from 50 µA to 20 mA. When biased at 5 mA, the device yields 0.8 nV/√ Hz of input-referred noise, giving ultra-low noise performance with extremely high input impedance (> 1 TΩ). The JFE150 also features integrated diodes connected to separate clamp nodes to provide protection without the addition of high-leakage, nonlinear, external diodes.
The JFE150 can withstand a high drain-to-source voltage of 40 V, as well as gate-to-source and gate-to-drain voltages down to –40 V. The temperature range is specified from –40°C to +125°C. The device is offered in 5-pin SOT-23 and SC70 packages.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | JFE150 Ultra-Low-Noise, Low-Gate-Current, Audio, N-Channel JFET datasheet (Rev. B) | PDF | HTML | 2023年 4月 25日 |
| Certificate | JFE150EVM EU RoHS Declaration of Conformity (DoC) | 2022年 2月 28日 | ||
| User guide | JFE150EVM User's Guide | PDF | HTML | 2022年 2月 25日 | |
| Application note | JFE150 Ultra-Low-Noise Pre-Amp | PDF | HTML | 2021年 10月 6日 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
DIP-ADAPTER-EVM — DIP 轉接器評估模組
Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount ICs. You can connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits.
The (...)
JFE150 Ultra-Low Noise Piezoelectric Amplifier PSpice Reference Circuit
JFE150 Ultra-Low Noise Piezoelectric Amplifier TINA-TI Reference Circuit
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23 (DBV) | 5 | Ultra Librarian |
| SOT-SC70 (DCK) | 5 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。