LMK04906
- Ultralow RMS Jitter
Performance
- 100-fs RMS Jitter (12 kHz to 20 MHz)
- 123-fs RMS Jitter (100 Hz to 20 MHz)
- Dual Loop
PLLatinum™ PLL
Architecture
- PLL1
- Integrated Low-Noise Crystal Oscillator Circuit
- Holdover Mode when Input Clocks are
Lost
- Automatic or Manual Triggering/Recovery
- PLL2
- Normalized [1 Hz] PLL Noise Floor of –227 dBc/Hz
- Phase Detector Rate up to 155 MHz
- OSCin Frequency-doubler
- Integrated Low-Noise VCO
- PLL1
- 3 Redundant Input
Clocks with LOS
- Automatic and Manual Switch-Over Modes
- 50% Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
- LVPECL, LVDS, or LVCMOS Programmable Outputs
- Precision Digital Delay, Fixed or Dynamically Adjustable
- 25-ps Step Analog Delay Control.
- 6 Differential
Outputs. Up to 12 Single Ended.
- Up to 5 VCXO/Crystal Buffered Outputs
- Clock Rates of up to 2600 MHz
- 0-Delay Mode
- Three Default Clock Outputs at Power Up
- Multi-mode: Dual PLL, Single PLL, and Clock Distribution
- Industrial Temperature Range: –40 to 85 °C
- 3.15-V to 3.45-V Operation
- Package: 64-Pin WQFN (9 mm × 9 mm × 0.8 mm)
The LMK04906 is the industry’s highest performance clock jitter attenuator with superior clock jitter cleaning, generation, and distribution with advanced features to meet high performance timing application needs.
The LMK04906 accepts 3 clock inputs ranging from 1 kHz to 500 MHz and generates 6 unique clock output frequencies ranging from 284 kHz to 2.6 GHz. The LMK04906 can also buffer a crystal or VCXO to generate a 7th unique clock frequency.
The device provides virtually all frequency translation combinations required for SONET, Ethernet, Fibre Channel and multi-mode Wireless Base Stations.
The LMK04906 input clock frequency and clock multiplication ratio are programmable through a SPI interface.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | LMK04906 Ultralow Noise Clock Jitter Cleaner and Multiplier With 6 Programmable Outputs datasheet (Rev. F) | PDF | HTML | 2017/8/11 | ||
| 應用說明 | Using the LMK0480x/LMK04906 for Hitless Switching and Holdover | 2013/7/12 | ||||
| 應用說明 | AN-1939 Crystal Based Oscillator Design with the LMK04000 Family (Rev. A) | 2013/4/26 | ||||
| 設計指南 | Clock Conditioner Owner's Manual | 2006/11/10 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
LMK04906BEVAL — 具有雙路串接 PLL 和整合 2.5 GHz VCO 的三路輸入、七路輸出時鐘抖動清除器
The LMK04906 is the industry's highest performance clock conditioner with superior clock jitter cleaning, generation, and distribution with advanced features to meet next generation system requirements. The dual loop PLLatinum™ architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low (...)
CODELOADER — CodeLoader Device Register Programming v4.19.0
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | (...) |
CLOCKDESIGNTOOL — Clock Design Tool Software
時脈設計工具軟體可協助進行零件選擇、迴路濾波器設計，以及計時裝置解決方案模擬。當您輸入所需的輸出頻率和參考頻率 (選用) 時，此工具可提供符合指定需求、分頻器值和建議迴路濾波器的 TI 裝置，以將抖動降到最低。
CLOCKDESIGNTOOL 教學影片
我應該使用哪個軟體？
產品 | 迴路濾波器和裝置配置 + 模擬 | 模擬工具 | 裝置暫存器程式化 |
LMX24xx PLL 系列 | EasyPLL | ||
LMX25xx PLL+VCO 系列 | 時脈設計工具 | ||
LMK 抖動清除器及分配器 |
CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體
時鐘樹架構是一款時鐘樹合成工具，可根據您的系統需求產生時鐘樹解決方案，進而簡化您的設計流程。此工具可從廣泛的計時產品資料庫中汲取資料，產生系統級多晶片計時解決方案。
PLLATINUMSIM-SW — PLL 迴路濾波器、相位雜訊、鎖定時間與雜散模擬工具
PLLATINUMSIM-SW 為一模擬工具，可讓使用者建立 PLLatinum™ 積體電路的詳細設計和模擬，包括 LMX 系列的相位鎖定迴路 (PLL) 及合成器。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| WQFN (NKD) | 64 | Ultra Librarian |
訂購與品質
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。