PLL1707-Q1
- Qualified for Automotive Applications
- 27-MHz Master Clock Input
- Generated Audio System Clock
- SCKO0: 768 fS (fS = 44.1 kHz)
- SCKO1: 768 fS, 512 fS (fS = 48 kHz)
- SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)
- SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)
- Zero PPM Error Output Clocks
- Low Clock Jitter: 50 ps (Typical)
- Multiple Sampling Frequencies:
fS = 32, 44.1, 48, 64, 88.2, 96 kHz - 3.3-V Single Power Supply
- Parallel Control
- Package: 20-Pin SSOP (150 mil), Lead-Free Product
- APPLICATIONS
- HDD + DVD Recorders
- DVD Recorders
- HDD Recorders
- DVD Players
- DVD Add-On Cards for Multimedia PCs
- Digital HDTV Systems
- Set-Top Boxes
The PLL1707 is a low-cost phase-locked loop (PLL) multiclock generator. The PLL1707 can generate four system clocks from a 27-MHz reference input frequency. The clock outputs of the PLL1707 can be controlled by sampling frequency-control pins. The device gives customers both cost and space savings by eliminating external components and enables customers to achieve the very low-jitter performance needed for high performance audio DACs and/or ADCs. The PLL1707 is ideal for MPEG-2 applications that use a 27-MHz master clock such as DVD recorders, HDD recorders, DVD add-on cards for multimedia PCs, digital HDTV systems, and set-top boxes.
技術文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 1
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | PLL1707-Q1 3.3-V Dual PLL Multi-Clock Generator . datasheet (Rev. A) | 2011/3/29 |
設計與開發
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SSOP (DBQ) | 20 | Ultra Librarian |