首頁 邏輯和電壓轉換 電壓轉換器及電平移位器 電壓轉換器
首頁
邏輯和電壓轉換
電壓轉換器及電平移位器
電壓轉換器

SN54SC6T14-SEP

現行

Radiation-tolerant, 6 bit, inverting fixed-direction level translator with Schmitt-trigger inputs

立即訂購
產品規格表

SN54SC6T14-SEP

現行
產品規格表 立即訂購

產品詳細資料

Bits (#) 6 Data rate (max) (Mbps) 150 Topology Push-Pull Vin (min) (V) 1.2 Vin (max) (V) 5.5 Applications GPIO Features Balanced outputs, Over-voltage tolerant inputs, Single supply Prop delay (ns) 12.5 Technology family SCxT Supply current (max) (mA) 0.093 Rating Space Operating temperature range (°C) -55 to 125
Bits (#) 6 Data rate (max) (Mbps) 150 Topology Push-Pull Vin (min) (V) 1.2 Vin (max) (V) 5.5 Applications GPIO Features Balanced outputs, Over-voltage tolerant inputs, Single supply Prop delay (ns) 12.5 Technology family SCxT Supply current (max) (mA) 0.093 Rating Space Operating temperature range (°C) -55 to 125
TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm)
  • Vendor item drawing available, VID V62/24618
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2V to 5.5V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2V
        • 2.5V – Inputs from 1.8V
        • 3.3V – Inputs from 1.8V, 2.5V
        • 5.0V – Inputs from 2.5V, 3.3V
      • Down translation:

        • 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

        • 1.8-V – Inputs from 2.5V, 3.3V, 5.0V
        • 2.5V – Inputs from 3.3V, 5.0V
        • 3.3V – Inputs from 5.0V
  • 5.5V tolerant input pins
  • Output drive up to 25 mA AT 5V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification
  • Vendor item drawing available, VID V62/24618
  • Total ionizing dose characterized at 30 krad (Si)
    • Total ionizing dose radiation lot acceptance testing (TID RLAT) for every wafer lot to 30 krad (Si)
  • Single-event effects (SEE) characterized:
    • Single event latch-up (SEL) immune to linear energy transfer (LET) = 43 MeV-cm2 /mg
    • Single event transient (SET) characterized to 43 MeV-cm2 /mg
  • Wide operating range of 1.2V to 5.5V
  • Single-supply translating gates at 5/3.3/2.5/1.8/1.2V VCC
    • TTL compatible inputs:
      • Up translation:
        • 1.8-V – Inputs from 1.2V
        • 2.5V – Inputs from 1.8V
        • 3.3V – Inputs from 1.8V, 2.5V
        • 5.0V – Inputs from 2.5V, 3.3V
      • Down translation:

        • 1.2V – Inputs from 1.8V, 2.5V, 3.3V, 5.0V

        • 1.8-V – Inputs from 2.5V, 3.3V, 5.0V
        • 2.5V – Inputs from 3.3V, 5.0V
        • 3.3V – Inputs from 5.0V
  • 5.5V tolerant input pins
  • Output drive up to 25 mA AT 5V
  • Latch-up performance exceeds 250 mA per JESD 17
  • Space enhanced plastic (SEP)
    • Controlled baseline
    • Gold bondwire
    • NiPdAu lead finish
    • One assembly and test site
    • One fabrication site
    • Military (–55°C to 125°C) temperature range
    • Extended product life cycle
    • Product traceability
    • Meets NASAs ASTM E595 outgassing specification

The SN54SC6T14-SEP device contains six independent Inverters with Schmitt-trigger inputs and extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8-V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).

The SN54SC6T14-SEP device contains six independent Inverters with Schmitt-trigger inputs and extended voltage operation to allow for level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8-V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2V input to 1.8V output or 1.8V input to 3.3V output). Additionally, the 5V tolerant input pins enable down translation (for example 3.3V to 2.5V output).
filter 尋找其它 電壓轉換器
下載 觀看有字幕稿的影片 影片

技術文件

找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 8
重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN54SC6T14-SEP Radiation Tolerant, Hex Schmitt-Trigger Inverters With Integrated Translation datasheet PDF | HTML 2023/1/20
* 輻射及可靠性報告 SN54SC6T14-SEP Production Flow and Reliability Report PDF | HTML 2024/4/10
* 輻射及可靠性報告 SN54SC6T07-SEP Single Event Effects Radiation Report PDF | HTML 2024/2/21
* 輻射及可靠性報告 SN54SC6T14-SEP Total Ionizing Dose (TID) Radiation Report PDF | HTML 2024/2/12
應用說明 Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024/10/2
Application brief TI Space Enhanced Plastic Logic Overview and Applications in Low-Earth Orbit Satellite Platforms PDF | HTML 2024/9/10
應用說明 Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024/7/12
應用說明 Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024/7/3

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
支援產品和硬體
有庫存
限制：
??asset.out-of-stock-ti_zh_TW??
無法提供
參考設計

TIDA-050088 — 適用於 Versal AI Edge 的耐輻射電源參考設計

這是針對 AMD Versal™ AI Edge XQRVE2302 所設計的耐輻射電源架構參考設計。Versal Edge 是適用於航太應用的採用型系統單晶片 (SoC)，能以小尺寸實現高效能。穩固的電力輸送是在航太環境中充分運用此設計的關鍵。此電源設計採用多個裝置為各種軌供電，並搭配時序控制器，來適當排序及監控軌。
支援產品和硬體
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 14 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片