SN64BCT25244
- State-of-the-Art BiCMOS Design Significantly Reduces ICCZ
- High-Impedance State During Power Up and Power Down
- ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
- Designed to Facilitate Incident-Wave Switching for Line Impedances of 25 or Greater
- Distributed VCC and GND Pins Minimize Noise Generated by the Simultaneous Switching of Outputs
- Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
The SN64BCT25244 is a 25- octal buffer and line driver designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.
When the output-enable (1 and 2) inputs are low, the device transmits data from the A inputs to the Y outputs. When 1 and 2 are high, the outputs are in the high-impedance state.
This buffer/driver is capable of sinking 188-mA IOL, which facilitates switching 25- transmission lines on the incident wave. The distributed VCC and GND pins minimize switching noise for more reliable system operation.
The outputs are in a high-impedance state during power up and power down while the supply voltage value is less than approximately 3 V.
The SN64BCT25244 is characterized for operation from -40°C to 85°C and 0°C to 70°C.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 25-Ohm Octal Buffer/Driver With 3-State Outputs datasheet | 1994年 1月 1日 | |
Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 2021年 7月 26日 | ||
Selection guide | Logic Guide (Rev. AB) | 2017年 6月 12日 | ||
Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 2015年 12月 2日 | ||
User guide | LOGIC Pocket Data Book (Rev. B) | 2007年 1月 16日 | ||
Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 2004年 7月 8日 | ||
Application note | TI IBIS File Creation, Validation, and Distribution Processes | 2002年 8月 29日 | ||
Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 1997年 8月 1日 | ||
Application note | Designing With Logic (Rev. C) | 1997年 6月 1日 | ||
Application note | Input and Output Characteristics of Digital Integrated Circuits | 1996年 10月 1日 | ||
Application note | Live Insertion | 1996年 10月 1日 |
設計與開發
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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 引腳 | 下載 |
---|---|---|
SOIC (DW) | 24 | 檢視選項 |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
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- 材料內容
- 資格摘要
- 進行中可靠性監測
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