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邏輯和電壓轉換
正反器、鎖存器和暫存器
D 型正反器

SN74AUP1G74

現行

低功耗單路正緣觸發 D 型正反器

立即訂購
產品規格表

SN74AUP1G74

現行
產品規格表 立即訂購

產品詳細資料

Number of channels 1 Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 160 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 1 Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 160 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
DSBGA (YFP) 8 1.8 mm² 1 x 1.8 DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 UQFN (RSE) 8 2.25 mm² 1.5 x 1.5 VSSOP (DCU) 8 6.2 mm² 2 x 3.1 X2SON (DQE) 8 1.4 mm² 1.4 x 1
  • Available in the Texas Instruments NanoStar Package
  • Low Static-Power Consumption: ICC = 0.9 μA Maximum
  • Low Dynamic-Power Consumption: Cpd = 5.5 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise – Overshoot and Undershoot < 10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

    • NanoStar Is a trademark of Texas Instruments. All other trademarks are the property of their respective owners

  • APPLICATIONS
    • Servers
    • LED Displays
    • Network Switches
    • Telecom Infrastructure
    • Motor Drivers
    • I/O Expanders
    •
  • Available in the Texas Instruments NanoStar Package
  • Low Static-Power Consumption: ICC = 0.9 μA Maximum
  • Low Dynamic-Power Consumption: Cpd = 5.5 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise – Overshoot and Undershoot < 10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 5 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)

    • NanoStar Is a trademark of Texas Instruments. All other trademarks are the property of their respective owners

  • APPLICATIONS
    • Servers
    • LED Displays
    • Network Switches
    • Telecom Infrastructure
    • Motor Drivers
    • I/O Expanders
    •

    The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in ).

    The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in ).
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    類型 標題 日期
    * Data sheet SN74AUP1G74 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. D) PDF | HTML 2015年 12月 29日
    Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 2022年 12月 15日
    Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 2019年 5月 22日
    Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
    Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
    Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
    Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日

    設計與開發

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    開發板

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    靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
    使用指南: PDF
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    Design guide: PDF
    電路圖: PDF
    參考設計

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    Design guide: PDF
    電路圖: PDF
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    Design guide: PDF
    電路圖: PDF
    參考設計

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    電路圖: PDF
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    Design guide: PDF
    電路圖: PDF
    封裝 針腳 CAD 符號、佔位空間與 3D 模型
    DSBGA (YFP) 8 Ultra Librarian
    DSBGA (YZP) 8 Ultra Librarian
    UQFN (RSE) 8 Ultra Librarian
    VSSOP (DCU) 8 Ultra Librarian
    X2SON (DQE) 8 Ultra Librarian
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    訂購與品質

    內含資訊：
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    • 鉛塗層/球物料
    • MSL 等級/回焊峰值
    • MTBF/FIT 估算值
    • 材料內容
    • 認證摘要
    • 進行中持續性的可靠性監測
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