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SN74AUP2G14

現行

具施密特觸發器輸入的 2 通道 0.8-V 至 3.6-V 低功耗逆變器

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產品規格表

SN74AUP2G14

現行
產品規格表 立即訂購

產品詳細資料

Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 10 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Number of channels 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 10 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YFP) 6 1.4000000000000001 mm² 1 x 1.4000000000000001 SOT-SC70 (DCK) 6 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in the Texas Instruments NanoStar™ package
  • Low static-power consumption (ICC = 0.9µA maximum)
  • Low dynamic-power consumption (Cpd = 4.3pF typical at 3.3V)
  • Low input capacitance (Ci = 1.5pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Wide operating VCC range of 0.8V to 3.6V
  • Optimized for 3.3V operation
  • 3.6V I/O tolerant to support mixed-mode signal Operation
  • tpd = 4.3ns maximum at 3.3V
  • Suitable for point-to-point applications
  • Latch-up performance exceeds 100mA Per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)
  • Available in the Texas Instruments NanoStar™ package
  • Low static-power consumption (ICC = 0.9µA maximum)
  • Low dynamic-power consumption (Cpd = 4.3pF typical at 3.3V)
  • Low input capacitance (Ci = 1.5pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Wide operating VCC range of 0.8V to 3.6V
  • Optimized for 3.3V operation
  • 3.6V I/O tolerant to support mixed-mode signal Operation
  • tpd = 4.3ns maximum at 3.3V
  • Suitable for point-to-point applications
  • Latch-up performance exceeds 100mA Per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8V to 3.6V, resulting in increased battery life (see Figure 5-1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 5-2).

The SN74AUP2G14 contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8V to 3.6V, resulting in increased battery life (see Figure 5-1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 5-2).

The SN74AUP2G14 contains two inverters and performs the Boolean function Y = A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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類型 標題 日期
* Data sheet SN74AUP2G14 Low-Power Dual Schmitt-Trigger Inverter datasheet (Rev. D) PDF | HTML 2025年 6月 1日
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025年 11月 13日
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML 2025年 4月 17日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日

設計與開發

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開發板

5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組

靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南: PDF
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開發板

5-8-NL-LOGIC-EVM — 支援 5 至 8 針腳 DPW、DQE、DRY、DSF、DTM、DTQ 和 DTT 封裝的通用邏輯和轉譯 EVM

支援任何具 DTT、DRY、DPW、DTM、DQE、DQM、DSF 或 DTQ 封裝的邏輯或轉換裝置之通用 EVM。可實現靈活評估的電路板設計。

使用指南: PDF | HTML
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模擬型號

SN74AUP2G14 Behavioral SPICE Model

SCEM674.ZIP (7 KB) - PSpice Model
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
DSBGA (YFP) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
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