SN74LVC126A
- Operates from 1.65V to 3.6V
- Specified from –40°C to +125°C
- Inputs accept voltages up to 5.5V
- Maximum tpd of 4.7ns at 3.3V
- Typical VOLP (output ground bounce), <0.8V at VCC = 3.3V, TA = 25°C
- Typical VOHV (output VOH undershoot), >2V at VCC = 3.3V, TA = 25°C
- Latch-up performance exceeds 250mA per JESD 17
The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation.
The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.
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封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
SOIC (D) | 14 | Ultra Librarian |
SOP (NS) | 14 | Ultra Librarian |
SSOP (DB) | 14 | Ultra Librarian |
TSSOP (PW) | 14 | Ultra Librarian |
TVSOP (DGV) | 14 | Ultra Librarian |
VQFN (RGY) | 14 | Ultra Librarian |
WQFN (BQA) | 14 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點