產品規格表
SN74LVC1G125B-EP
- Operating range from 1.1V to 5.5V
- 5.5V tolerant input pins
- Supports standard pinouts
- Latch-up performance exceeds 100mAper JESD 78
- Supports defense and aerospace applications:
- Controlled baseline
- One assembly and test site
- One fabrication site
- Extended product life cycle
- Product traceability
The SN74LVC1G125B-EP device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable ( OE) input is high. When OE is low, true data is passed from the A input to the Y output.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SN74LVC1G125B-EP Octal Buffers With 3-Stet Outputs datasheet | PDF | HTML | 2026/6/29 | ||
| * | 輻射及可靠性報告 | SN74LVC1G125B-EP Enhanced Product Qualification and Reliability Report | PDF | HTML | 2026/3/6 |
設計與開發
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開發板
5-8-LOGIC-EVM — 適用於 5 針腳至 8 針腳 DCK、DCT、DCU、DRL 和 DBV 封裝的通用邏輯評估模組
靈活的 EVM 旨在支援任何針腳數為 5 至 8 支且採用 DCK、DCT、DCU、DRL 或 DBV 封裝的裝置。
使用指南:
PDF
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOT-23 (DBV) | 5 | Ultra Librarian |