首頁 邏輯和電壓轉換 電壓轉換器及電平移位器 電壓轉換器
首頁
邏輯和電壓轉換
電壓轉換器及電平移位器
電壓轉換器

SN74LVC4245A

現行

具有 3 態輸出的八路匯流排收發器和 3.3-V 至 5-V 移位器

立即訂購
產品規格表

SN74LVC4245A

現行
產品規格表 立即訂購

產品詳細資料

Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (min) (V) 2.7 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable Prop delay (ns) 6.7 Technology family LVC Supply current (max) (mA) 0.13 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 8 Data rate (max) (Mbps) 200 Topology Push-Pull Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (min) (V) 2.7 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Output enable Prop delay (ns) 6.7 Technology family LVC Supply current (max) (mA) 0.13 Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 24 159.65 mm² 15.5 x 10.3 SSOP (DB) 24 63.96 mm² 8.2 x 7.8 TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • 8-bit direction controlled translating bus transceiver
  • 5.5V on A port and 2.7V to 3.6V on B port
  • High drive strength for heavier loading conditions
    • 24mA at 3V supply
  • Robust, glitch-free power supply sequencing
  • VCC isolation and VCC disconnect feature
    • If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • Ioff supports Partial-Power-Down node operation
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating temperature range -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model
    • 1000V Charged-Device Model
  • Compatible with SN74LVC4245
  • 8-bit direction controlled translating bus transceiver
  • 5.5V on A port and 2.7V to 3.6V on B port
  • High drive strength for heavier loading conditions
    • 24mA at 3V supply
  • Robust, glitch-free power supply sequencing
  • VCC isolation and VCC disconnect feature
    • If either VCC input is below 100mV or left floating, all I/O outputs are disabled and become high impedance
  • Control inputs VIH/VIL levels are referenced to VCCA voltage
  • Ioff supports Partial-Power-Down node operation
  • Latch-up performance exceeds 250mA per JESD 17
  • Operating temperature range -40°C to 85°C
  • ESD protection exceeds JESD 22
    • 2000V Human-Body Model
    • 1000V Charged-Device Model
  • Compatible with SN74LVC4245

This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has VCCB, which is set at 3.3V, and A port has VCCA, which is set at 5V. This allows for translation from a 3.3V to a 5V environment, and vice versa.

The SN74LVC4245A device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.

The SN74LVC4245A device terminal out allows the designer to switch to a normal all 3.3V or all 5V 20-terminal SN74LVC4245 device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A device to align with the conventional ’245 terminal out.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling the outputs.

This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has VCCB, which is set at 3.3V, and A port has VCCA, which is set at 5V. This allows for translation from a 3.3V to a 5V environment, and vice versa.

The SN74LVC4245A device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.

The SN74LVC4245A device terminal out allows the designer to switch to a normal all 3.3V or all 5V 20-terminal SN74LVC4245 device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the SN74LVC4245A device to align with the conventional ’245 terminal out.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature is designed so that if either VCCA or VCCB is less than 100mV, both I/O ports enter a high-impedance state by disabling the outputs.
filter 尋找其它 電壓轉換器
下載 觀看有字幕稿的影片 影片

技術文件

star =TI 所選的此產品重要文件
找不到結果。請清除您的搜尋條件，然後再試一次。
檢視所有 31
重要文件 類型 標題 格式選項 日期
* Data sheet SN74LVC4245A Octal Bus Transceiver and 3.3V to 5V Shifter With 3-State Outputs datasheet (Rev. K) PDF | HTML 2026年 5月 29日
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025年 11月 13日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Voltage Translation Buying Guide (Rev. A) 2021年 4月 15日
Selection guide Little Logic Guide 2018 (Rev. G) 2018年 7月 6日
Application note How to Select Little Logic (Rev. A) 2016年 7月 26日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Product overview Design Summary for WCSP Little Logic (Rev. B) 2004年 11月 4日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 2003年 11月 6日
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 2002年 12月 18日
Application note Texas Instruments Little Logic Application Report 2002年 11月 1日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002年 6月 13日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 2002年 3月 27日
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 1997年 12月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note LVC Characterization Information 1996年 12月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Design guide Low-Voltage Logic (LVC) Designer's Guide 1996年 9月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

使用指南: PDF | HTML
TI.com 無法提供
模擬型號

SN74LVC4245A IBIS Model

SCAM009.ZIP (30 KB) - IBIS Model
下載
封裝 針腳 CAD 符號、佔位空間與 3D 模型
SOIC (DW) 24 Ultra Librarian
SSOP (DB) 24 Ultra Librarian
TSSOP (PW) 24 Ultra Librarian
適用 TI 的評估品項標準條款與條件。

訂購與品質

內含資訊：
  • RoHS
  • REACH
  • 產品標記
  • 鉛塗層/球物料
  • MSL 等級/回焊峰值
  • MTBF/FIT 估算值
  • 材料內容
  • 認證摘要
  • 進行中的可靠性監測
內含資訊：
  • 晶圓廠位置
  • 組裝地點

支援與培訓

內含 TI 工程師技術支援的 TI E2E™ 論壇

以英文檢視所有論壇主題

內容係由 TI 和社群貢獻者依「現狀」提供，且不構成 TI 規範。檢視使用條款。

若有關於品質、封裝或訂購 TI 產品的問題，請參閱 TI 支援。​​​​​​​​​​​​​​

影片