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TPS543B20

現行

具有適應性內部補償功能的 4-V 至 19-V、25-A 同步 SWIFT™ 降壓轉換器

產品詳細資料

Rating Catalog Topology Buck Iout (max) (A) 25 Vin (max) (V) 19 Vin (min) (V) 4 Vout (max) (V) 5.5 Vout (min) (V) 0.6 Features Adjustable current limit, Differential Remote Sense, Enable, Forced PWM, Frequency synchronization, Over Current Protection, Phase Interleaving, Power good, Pre-Bias Start-Up, Soft Start Adjustable, Synchronous Rectification, UVLO Fixed Control mode ACM/AECM Operating temperature range (°C) -40 to 125 Iq (typ) (A) 0.0043 Duty cycle (max) (%) 70
Rating Catalog Topology Buck Iout (max) (A) 25 Vin (max) (V) 19 Vin (min) (V) 4 Vout (max) (V) 5.5 Vout (min) (V) 0.6 Features Adjustable current limit, Differential Remote Sense, Enable, Forced PWM, Frequency synchronization, Over Current Protection, Phase Interleaving, Power good, Pre-Bias Start-Up, Soft Start Adjustable, Synchronous Rectification, UVLO Fixed Control mode ACM/AECM Operating temperature range (°C) -40 to 125 Iq (typ) (A) 0.0043 Duty cycle (max) (%) 70
LQFN-CLIP (RVF) 40 35 mm² (7 mm × 5 mm)
  • Internally-Compensated Advanced Current Mode Control 25-A POL
  • Input Voltage Range: 4 V to 19 V
  • Output Voltage Range: 0.6 V to 5.5 V
  • Integrated 4.1/1.9-mΩ Stacked NexFET™ Power Stage With Lossless Low-Side Current Sensing
  • Fixed Frequency - Synchronization to an External Clock and/or Sync Out
  • Pin Strapping Programmable Switching Frequency
    • 300 kHz to 2 MHz for Standalone
    • 300 kHz to 1 MHz for Stackable
  • Stack 2× for up to 50 A With Current Share, Voltage Share, and CLK Sync
  • Pin Strapping Programmable Reference from 0.6 V to 1.1 V With 0.5% Accuracy
  • Differential Remote Sensing
  • Safe Start-Up into Prebiased Output
  • High-Accuracy Hiccup Current Limit
  • Asynchronous Pulse Injection (API) and Body Braking
  • 40-pin, 5-mm × 7-mm LQFN Package with 0.5-mm Pitch and Single Thermal Pad
  • Create a Custom Design Using the TPS543B20 With the WEBENCH® Power Designer
  • Internally-Compensated Advanced Current Mode Control 25-A POL
  • Input Voltage Range: 4 V to 19 V
  • Output Voltage Range: 0.6 V to 5.5 V
  • Integrated 4.1/1.9-mΩ Stacked NexFET™ Power Stage With Lossless Low-Side Current Sensing
  • Fixed Frequency - Synchronization to an External Clock and/or Sync Out
  • Pin Strapping Programmable Switching Frequency
    • 300 kHz to 2 MHz for Standalone
    • 300 kHz to 1 MHz for Stackable
  • Stack 2× for up to 50 A With Current Share, Voltage Share, and CLK Sync
  • Pin Strapping Programmable Reference from 0.6 V to 1.1 V With 0.5% Accuracy
  • Differential Remote Sensing
  • Safe Start-Up into Prebiased Output
  • High-Accuracy Hiccup Current Limit
  • Asynchronous Pulse Injection (API) and Body Braking
  • 40-pin, 5-mm × 7-mm LQFN Package with 0.5-mm Pitch and Single Thermal Pad
  • Create a Custom Design Using the TPS543B20 With the WEBENCH® Power Designer

The TPS543B20 employs an internally compensated emulated peak-current-mode control, with a clock synchronizable, fixed-frequency modulator for EMI-sensitive POL. The internal integrator and directly amplifying ramp tracking loop eliminate the need for external compensation over a wide range of frequencies thereby making the system design flexible, dense, and simple. Optional API and body braking help improve transient performance by significantly reducing undershoot and overshoot, respectively. Integrated NexFET™ MOSFETs with low-loss switching facilitate high efficiency and deliver up to 25 A in a 5-mm × 7-mm PowerStack™ package with a layout friendly thermal pad. Two TPS543B20 devices can be stacked together to provide up to 50-A point-of-load.

The TPS543B20 employs an internally compensated emulated peak-current-mode control, with a clock synchronizable, fixed-frequency modulator for EMI-sensitive POL. The internal integrator and directly amplifying ramp tracking loop eliminate the need for external compensation over a wide range of frequencies thereby making the system design flexible, dense, and simple. Optional API and body braking help improve transient performance by significantly reducing undershoot and overshoot, respectively. Integrated NexFET™ MOSFETs with low-loss switching facilitate high efficiency and deliver up to 25 A in a 5-mm × 7-mm PowerStack™ package with a layout friendly thermal pad. Two TPS543B20 devices can be stacked together to provide up to 50-A point-of-load.

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技術文件

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 TPS543B20 4-VIN to 19-VIN, 25-A Stackable, Synchronous Step-Down SWIFT™ Converter With Adaptive Internal Compensation datasheet (Rev. B) PDF | HTML 2018/3/28
類比設計期刊 Control-Mode Quick Reference Guide (Rev. B) PDF | HTML 2023/8/29
應用說明 Point-of-Load Solutions for Network Interface Cards (NIC) PDF | HTML 2021/9/8
應用說明 DC/DC Converter Solutions for Hardware Accelerators in Data Center Applications (Rev. A) PDF | HTML 2021/5/4
應用說明 Non-Isolated Point-of-Load Solutions for Tiger Lake in PC Applications (Rev. B) PDF | HTML 2021/4/29
選擇指南 Buck Converter Quick Reference Guide (Rev. B) 2021/4/8
技術文章 3 big benefits of small cells PDF | HTML 2020/5/26
應用說明 Non-Isolated Point-of-Load Solutions for Elkhart Lake in Industrial PC App. (Rev. A) PDF | HTML 2020/5/21
應用說明 Point-of-Load Solutions for Data Center App Implementing VR13.HC Vccin Spec (Rev. A) PDF | HTML 2020/1/8
白皮書 Small Cells, Big Impact: Designing Power Soutions for 5G Applications 2019/6/26
應用說明 DC/DC Point-of-load Power Solutions for Wired Networking Switch Systems 2018/12/11
白皮書 Internally compensated advanced current mode (ACM) (Rev. A) 2018/12/7
應用說明 Solve Point-of-Load Power Design Challenges: Single Board Computer Applications 2018/8/24
技術文章 Why are there so many control modes for step-down DC/DC converters and controllers PDF | HTML 2018/4/4
技術文章 Powering FPGAs – Improving overshoot of voltage regulators for Intel Arria 10 and PDF | HTML 2018/2/8
技術文章 Powering FPGAs – Improving undershoot of voltage regulators with asynchronous puls PDF | HTML 2018/2/2
技術文章 Powering FPGAs - What to consider with Xilinx UltraScale+ FPGAs PDF | HTML 2018/1/29
類比設計期刊 Understanding thermal-resistance specification of DC/DC convert. w/ MOSFETs 2018/1/4
技術文章 Lightning-fast internally-compensated ACM topology – what can it do for you? PDF | HTML 2017/5/18

設計與開發

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開發板

TPS543B20EVM-054 — 25-A、固定頻率非補償可堆疊同步降壓轉換器評估模組

TPS543B20EVM-054 的設計旨在幫助使用者輕鬆評估及測試 TPS543B20 降壓轉換器的運作及功能。EVM 將 4-V 至 19-V 輸入電壓轉換為穩定的 0.9-V 輸出電壓,可在 5-mm x 7-mm QFN 封裝中提供高達 25A 的電流。EVM 配備方便的測試點,可用於測量重要波形。

使用指南: PDF | HTML
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模擬型號

TPS543B20 PSpice Transient Model

SLUM590.ZIP (128 KB) - PSpice 模型
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計算工具

SLURB00 — TPS543B20 TPS543C20A TPS543C20 Excel Calculator Tool and Checklist

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參考設計

PMP22194 — 具備可調整負輸出電壓參考設計的同步反相降壓升壓轉換器

此參考設計使用具有內部頂部和底部 FET 的同步降壓穩壓器,該穩壓器配置為同步反相降壓升壓轉換器,以提供 -0.2 V 和 -0.6 V 之間能夠提供最大 15 A 電流至負載的可調輸出。輸出電壓由外部 PWM 訊號或類比電壓訊號進行調整。

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參考設計

TIPA-050005 — 適用於 PC 應用中 Tiger Lake 的非隔離負載點解決方案

Intel® Tiger Lake 微架構等先進處理器和平台需要負載點 (POL) 解決方案,來滿足記憶體、低功耗 CPU 軌,以及一系列充電電池或 12V 輸入匯流排的 3.3V 和 5V 軌需求。

 

此電源供應設計以最新 DC/DC 轉換器為亮點,展示可因應 PC 應用中一般 Tiger Lake 電源需求的功能。

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封裝 針腳 CAD 符號、佔位空間與 3D 模型
LQFN-CLIP (RVF) 40 Ultra Librarian

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