VSP1221
- 12-Bit, 21-MSPS, Analog-to-Digital Converter
- Low Power: 70 mW Minimum Power-Down Mode: 4 mW
- Low Input-Referred Noise: 75-dB SNR Typical at 0-dB Gain
- Novel Optical-Black (OB) Calibration
- Low-Aperture Delay
- Single 3-V Supply Operation
- DNL: <±0.5 LSB and <±1.5 LSB Typical at 0-dB Gain
- Programmable-Gain Range: 0 dB to 36 dB, Gain Resolution of 0.05 dB/Step
- 48-Pin TQFP Package
- applications
- Digital Still Camera
- Digital Video Camera
The VSP1221 is a highly-integrated mixed-signal IC used for signal conditioning and analog-to-digital conversion at the output of a CCD array. The IC has a correlated double sampler (CDS) and an analog programmable-gain amplifier (PGA) stage followed by an analog-to-digital converter (ADC) and a digital PGA stage. The CDS is used to sample the CCD signal and is followed by the analog PGA stage. The ADC is a 12-bit, 21-MSPS pipelined ADC. The digital PGA provides further amplification.
Additionally, there is an offset calibration loop for optical-black correction. The optical-black reference level is user-programmable. The chip also has two eight-bit digital-to-analog converters (DAC) for external analog settings.
The chip has a serial port for configuring internal control registers.
The VSP1221 is available in a 48-pin TQFP package and operates from a single 3-V power supply.
技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 12-Bit, 21-MSPS, UltraLow-Power CCD Signal Processor datasheet (Rev. B) | 2014年 4月 16日 | |
| White paper | Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) | PDF | HTML | 2024年 4月 30日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| TQFP (PFB) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點