The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-VVCC operation. This device features dual line drivers with 3-state outputs.The outputs are disabled when the associated output-enable (OE) input ishigh.
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To ensure the high-impedance state during power up or power down,OE should be tied to VCC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of thedriver.
This device is fully specified for partial-power-down applications usingIoff. The Ioff circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.