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High Speed CMOS Logic 4-Bit Binary Ripple Counter

Same as: CD74HC93EE4   This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

Inventory: 5,580  

Quality information

RoHS Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow N/A for Pkg Type
Quality, reliability
& packaging information

Information included:

  • RoHS
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Packaging information

Package | Pins Package qty | Carrier: Operating temperature range (℃)
PDIP (N) | 14 25 | TUBE
-55 to 125
Package | Pins PDIP (N) | 14
Package qty | Carrier: 25 | TUBE
Operating temperature range (℃) -55 to 125
View TI packaging information

Features for the CD74HC93

  • Can Be Configured to Divide By 2, 8, and 16
  • Asynchronous Master Reset
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL , VOH

Data sheet acquired from Harris Semiconductor

Description for the CD74HC93

The CD74HC93 and CD74HCT93 are high-speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL). These 4-bit binary ripple counters consist of four master-slave flip-flops internally connected to provide a divide-by-two section and a divide-by-eight section. Each section has a separate clock input (CP0\ and CP1\) to initiate state changes of the counter on the HIGH to LOW clock transition. State changes of the Qn outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used for clocks or strobes.

A gated AND asynchronous master reset (MR1 and MR2 is provided which overrides both clocks and resets (clears) all flip-flops.

Because the output from the divide by two section is not internally connected to the succeeding stages, the device may be operated in various counting modes.

In a 4-bit ripple counter the output Q0 must be connected externally to input CP1\. The input count pulses are applied to clock input CP0\. Simultaneous frequency divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as shown in the function table. As a 3-bit ripple counter the input count pulses are applied to input CP1\.

Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with the reset of the 3-bit ripple-through counter.


Qty Price (USD)
1-99 1.315
100-249 1.086
250-999 0.78
1,000+ 0.587