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Dual J-K Flip-Flops With Clear

Inventory: 2,227

Download data sheet for SN74LS107A
  |   View additional information for SN74LS107A

Packaging information

Package | Pins PDIP (N) | 14
Operating temperature range (°C) C (0 to 70)
Package qty | Carrier: 25 | TUBE
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Quality information

RoHS Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow N/A for Pkg Type
Material content View
DPPM / MTBF / Fit rate View
Qualification summary View
Ongoing reliability monitoring View
Device marking View


  • Package Options Include Plastic “Small Outline Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPs
  • Dependable Texas Instruments Quality and Reliability



The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.


Qty Price
1-99 $1.508
100-249 $1.245
250-999 $0.894
1,000+ $0.673