The three-phase inverter is realized using six CSD18510Q5B power MOSFETs as shown in Figure 3-1. The MOSFET is rated for a maximum drain-to-source voltage of 40 V and a peak current of 400 A. The design has the provision to use the RC snubber across all the FETs. The voltage ringing is expected to be maximum across the FETs due to diode reverse recovery. With bipolar control, a snubber is not necessarily required across all the FETs and the need depends on the current direction, PWM strategy, and diode reverse recovery.

The snubber capacitor is selected as approximately several times the output capacitance of the FET, which is 832 pF in this design. The snubber resistor value is tuned during board testing to sufficiently damp the VDS switching overshoot ringing during switching. C30, C31, and C32 are decoupling capacitors between the VDC input and the source terminal of the bottom FET of each leg. This decoupling capacitor reduces the ringing in the supply lines caused by the parasitic inductance added by the sense resistor and the power track. The design also has an optional external capacitance between the gate to source of each FET, to reduce the gate pick up or gate ringing during switching.