TIDUF36A May   2023  – December 2023 DRV8328

 

  1.   1
  2.   Description
  3.   Resources
  4.   Features
  5.   Applications
  6.   6
  7. 1System Description
    1. 1.1 Key System Specifications
  8. 2System Overview
    1. 2.1 Block Diagram
    2. 2.2 Design Considerations
    3. 2.3 Highlighted Products
      1. 2.3.1 DRV8328C
      2. 2.3.2 MSPM0G1507
      3. 2.3.3 CSD18510Q5B
      4. 2.3.4 TMP61
  9. 3System Design Theory
    1. 3.1 Power Stage Design: Three-Phase Inverter
      1. 3.1.1 Selecting Sense Resistor
    2. 3.2 Power Stage Design: DRV8328 Gate Driver
      1. 3.2.1 DRV8328 Features
      2. 3.2.2 AVDD Linear Voltage Regulator (LDO)
    3. 3.3 Power Stage Design: MSPM0 Microcontroller
      1. 3.3.1 Low-Side Current Sensing With MSPM0G1507
      2. 3.3.2 Temperature Sensing
    4. 3.4 Power Stage Design: External Interface Options and Indications
      1. 3.4.1 Hall Sensor Interface
      2. 3.4.2 Input Power Voltage Monitoring
      3. 3.4.3 Motor Speed Control
      4. 3.4.4 Direction of Rotation: Digital Input
      5. 3.4.5 Programming Interface for MCU
      6. 3.4.6 Data Transmission
      7. 3.4.7 LED Indicators
      8. 3.4.8 Sleep Mode Entry Control
  10. 4Hardware, Software, Testing Requirements, and Test Results
    1. 4.1 Hardware Requirements
      1. 4.1.1 Hardware Board Overview
    2. 4.2 Software Requirements
    3. 4.3 Test Setup
    4. 4.4 Test Results
      1. 4.4.1 Functional Evaluation of DRV8328 Gate Driver
        1. 4.4.1.1 DRV8328 Linear Regulator Performance
        2. 4.4.1.2 Gate Drive Voltage Generated by Gate Driver
      2. 4.4.2 MOSFET Switching Waveforms
      3. 4.4.3 Current Open Loop Test
      4. 4.4.4 Current Open Loop Load Test
  11. 5Design and Documentation Support
    1. 5.1 Design Files
      1. 5.1.1 Schematics
      2. 5.1.2 BOM
    2. 5.2 Tools and Software
    3. 5.3 Documentation Support
    4. 5.4 Support Resources
    5. 5.5 Trademarks
  12. 6About the Author
  13. 7Revision History

4.4.2 MOSFET Switching Waveforms

Figure 4-5 shows the PWM scheme used in the reference design testing for trapezoidal control of the BLDC motor. The control is a six-step block commutation where PWM is applied to the top switch and the bottom switch is operated in active freewheeling during the positive phase winding current for 120° electrical period. The bottom MOSFET switch is kept continuously ON during the negative phase winding current for 120° electrical period.

  • CH2 (Cyan): High-side PWM
  • CH3 (Purple): Low-side PWM
GUID-20230515-SS0I-60TD-MM23-KW689WDDPKX9-low.pngFigure 4-5 Low- and High-Side FET PWM Generated by MCU

Figure 4-6 and Figure 4-7 show the VDS and VGS waveforms of the low-side and high-side MOSFETs The switching waveforms are captured with a 10-Ω gate resistor for each FET. Switching waveforms are clean without any overvoltage ringing.

  • CH1 (Blue): High-side VDS
  • CH2 (Cyan): High-side VGS
GUID-20230515-SS0I-CRHL-TDF4-8QR86SS5QKCX-low.pngFigure 4-6 High-Side VGS and VDS
  • CH1 (Blue): Low-side VGS
  • CH2 (Cyan): Low-side VDS
GUID-20230516-SS0I-P2HV-MTTW-HSGK9DBJFBDT-low.pngFigure 4-7 Low-Side VGS and VDS