TPS7H3301-SP
Strahlungsfester QMLV-LDO-Regler mit DDR-Terminierung, 2,3 bis 3,5 V Eingang, 3 A Senke und Quelle
TPS7H3301-SP
- 5962R14228(1):
- Radiation hardness assurance (RHA) qualified to total ionizing dose (TID) 100 krad(Si)
- Single event latch-up (SEL), single event gate rupture (SEGR), single event burnout (SEB) immune to LET = 70 MeV-cm2/mg(2)
- Single event transient (SET), single event functional interrupt (SEFI), and single event upset (SEU) characterized to 70 MeV-cm2/mg(2)
- Supports DDR, DDR2, DDR3, DDR3L, and DDR4 termination applications
- Input voltage: supports a 2.5-V and 3.3-V rail(3)
- Separate low-voltage input (VLDOIN) down to
0.9 V for improved power efficiency(3) - 3-A sink and source termination regulator includes droop compensation
- Enable input and power-good output for power supply sequencing
- VTT termination regulator
- Output voltage range: 0.5 to 1.75 V
- 3-A sink and source current
- Integrated precision voltage divider network with sense input
- Remote sensing (VTTSNS)
- VTTREF buffered reference
- ±15-mV accuracy
- ±10-mA sink and source current
- Undervoltage lockout (UVLO) and overcurrent limit (OCL) functionality integrated
The TPS7H3301-SP is a TID and SEE radiation-hardened double data rate (DDR) 3-A termination regulator with built-in VTTREF buffer. The regulator is specifically designed to provide a complete, compact, low-noise solution for space DDR termination applications such as single board computers, solid state recorders, and payload processing.
The TPS7H3301-SP supports DDR VTT termination applications using DDR, DDR2, DDR3, DDR4. The fast transient response of the TPS7H3301-SP VTT regulator allows for a very stable supply during read/write conditions. During transients, the fast tracking feature of the VTTREF supply minimizes any voltage offset between VTT/Vo and VTTREF. To enable simple power sequencing, both an enable input and a power-good output (PGOOD) have been integrated into the TPS7H3301-SP. The PGOOD output is open-drain so it can be tied to multiple open-drain outputs to monitor when all supplies have come into regulation. The enable signal can also be used to discharge VTT/Vo during suspend to RAM (S3) power down mode.
Technische Dokumentation
Design und Entwicklung
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TPS7H3301EVM-CVAL — TPS7H3301-SP DDR-Abschluss – Evaluierungsmodul
TPS7H3301-SP source/sink Double Data Rate (DDR) termination regulator designed to support system needs for low noise applications.
Integrated solution with reduced system solution size, improved efficiency, and simple system design integration.
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TPS7H3301-SP Unencrypted PSPICE Transient Model
Gehäuse | Pins | Herunterladen |
---|---|---|
CFP (HKR) | 16 | Optionen anzeigen |
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