Multiple clocks are created from one external master clock source in the ADS131A0x to create device configuration flexibility. The ADC operates from the internal system clock, ICLK, which is provided in one of three ways.
The system ICLK is passed through a second 3-bit clock divider (ICLK_DIV[2:0] in the CLK2 register) to create the modulator clock, MODCLK. MODCLK is used for timing of the delta-sigma (ΔΣ) modulator sampling and digital filter.
The interface operation mode determines the options for sourcing ICLK. When in asynchronous interrupt or synchronous master mode, generate ICLK by applying a direct external master clock signal to the XTAL1/CLKIN pin or by using a crystal oscillator across the XTAL1/CLKIN and XTAL2 pins. If directly applying a master clock to the XTAL1/CLKIN pin, leave XTAL2 floating. In synchronous slave mode, a free-running SCLK line can be connected directly into the ICLK_DIV block in place of the divided XTAL or CLKIN source. Use the CLKSRC bit in the CLK1 register to select between the XTAL1/CLKIN or SCLK input as the master clock source for the ADC. The CLKSRC bit must be set prior to powering up the ADC channels. Using SCLK as ICLK is useful in galvanic isolated applications to limit the digital I/O lines crossing the isolation barrier. Figure 35 shows the clock dividers and clocking names.