Figure 64 shows the relationship between DRDY, DOUT, DIN, and SCLK during data retrieval in synchronous master mode. The high-to-low DRDY transition from the ADS131A0x starts a data frame and indicates that new data are available. DIN and DOUT transition on the SCLK rising edge. After the LSB is shifted out DRDY returns high, completing the data frame. The ICLK speed must be fast enough to shift out the required bits before new data are available because ICLK determines the SCLK output rate, as described in the Serial Clock (SCLK) section. Tie the CS signal to the DONE signal in single device synchronous master mode.