SCLK is the SPI serial clock. Use SCLK to shift in commands on DIN and shift out data from the device on DOUT, similar to the description in the Asynchronous Interrupt Mode section.
If the SCLK source is free-running, the SCLK input signal can be set as the ADC ICLK, removing the need of a separate CLKIN. The CLKSRC bit in the CLK1 register controls the source for the ADC ICLK. The modulator clock is derived from the ICLK using the ICLK_DIV[2:0] bits in the CLK2 register; see Figure 35 for a diagram of how SCLK is routed into the device when serving as the ICLK. Setting SCLK as the internal ICLK requires that clocks are sent continuously without any delay or stop periods. Care must be taken to prevent glitches on SCLK at all times.