The digital filter receives the modulator output and decimates the data stream to create the final conversion result. The digital filter on each channel consists of a third-order sinc filter. The oversampling ratio (OSR) determines the number of samples taken to create the output data word, and is set by the modulator rate divided by the data rate (fMOD / fDATA). The OSR of the sinc filters is adjusted by the OSR[3:0] bits in the CLK2 register. The OSR setting is a global setting that affects all channels and, therefore, all channels operate at the same data rate in the device. By adjusting the OSR, tradeoffs can be made between noise and data rate to optimize the signal chain: filter more for lower noise (thus creating lower data rates), filter less for higher data rates.
The sinc filter is a variable decimation rate, third-order, low-pass filter. Data are supplied to this section of the filter from the modulator at the rate of fMOD. Equation 6 shows the scaled sinc3 filter Z-domain transfer function. As shown in Table 6, the integer N is the set OSR and the integer K is a scaling factor for OSR values that are not an integer power of 2.
Equation 7 shows the sinc filter frequency domain transfer function. As shown in Table 6, the integer N is the set OSR and the integer K is a scaling factor for OSR values that are not an integer power of 2.
|OSR (N)||K SCALING VALUE|
|800, 400, 200||0.9983778|
|4096, 2048, 1024, 512, 256, 128, 64, 32||1.0|
|768, 384, 192, 96, 48||1.00195313|
The sinc3 filter has notches (or zeroes) that occur at the output data rate and multiples thereof. At these frequencies, the filter has infinite attenuation. Figure 45 and Figure 46 illustrate the digital filter frequency response out to a normalized input frequency (fIN / fDATA) of 5 and 0.5, respectively. Figure 47, Figure 48, and Figure 49 illustrate the frequency response for OSR = 32, OSR = 512, and OSR = 4096 up to fMOD, respectively.
The K scaling factor for OSR values that are not an integer power of two adds a non-integer gain factor to the sinc3 frequency response across all frequencies. The host must account for the K scaling factor to obtain the ADC gain error given in the Electrical Characteristics table. Figure 50 overlays the digital filter frequency response for the three K scaling options in Table 6. Graph scaling is set to a narrow limit to show the small gain variation between OSR values.
The ADS131A0x immediately begins ADC conversions when powered up and brought out of standby mode using the WAKEUP command. The DRDY falling edge indicates when each ADC conversion completes. The sinc3 digital filter requires three conversion cycles to settle (tSETTLE), assuming the analog input has settled to its final value. The output data are not gated when the digital filter settles, meaning that the first two ADC conversion results show unsettled data from the filter path before settled data are available for the third ADC conversion. The first two unsettled ADC conversions, though unsettled, can be used for diagnostic purposes to ensure the ADC is coming out of standby as expected.
In addition to the sinc3 filter settling, the ADC requires an extra data period to report the conversion data. After the ADC accumulates the digital filter data, an additional data period is required for the ADC data to reach the DOUT buffer. Because of the digital filter settling and the DOUT buffer, the device requires four data periods to retrieve data from DOUT. Figure 51 shows the data ready behavior and time needed for the digital filter settling and data retrieval coming out of standby.
The digital filter uses a multiple stage linear-phase digital filter. Linear-phase filters exhibit constant delay time across all input frequencies (also known as constant group delay). This behavior results in zero-phase error when measuring multi-tone signals. For more information about group delay in delta-sigma ADCs, see the Accounting for delay from multiple sources in delta-sigma ADCs white paper.