Figure 98 shows a multiple device configuration where the first device is configured in synchronous master mode as indicated by the state of the M0 pin. The second ADS131A0x device and any additional devices are configured in synchronous slave mode. The DONE pin of each device connects to the CS pin of the subsequent device. In each case, after a device shifts out all of its data, the device deasserts DONE, selecting the subsequent device for communication. Tie the DONE pin of the last device to the CS pin of the first device to allow for an immediate second read back of conversion data in the case a data integrity test failed. The DOUT of a device whose contents are already shifted out assumes a high-impedance state, allowing the DOUT pins of all devices to be tied together. To send commands to specific devices, send the respective command of the device when that device is selected for communication. The DRDY output of the first device serves as the DRDY input to all other devices to synchronize conversions. DRDY also serves as the chip-select or frame sync signal for the host. SCLK is free running with the same frequency as ICLK in this configuration. Figure 99 illustrates an example interface timing diagram for this configuration.
NOTE:(1) denotes device 1, (2) denotes device 2, and (N) denotes device N.