Each ADS131A0x channel has two integrated comparators to detect overrange and underrange conditions on the input signals. Use the COMP_TH[2:0] bits in the A_SYS_CFG register to set a high and low threshold level using a 3-bit digital-to-analog converter (DAC). This threshold voltage is compared to the voltage on the input pins. The voltage monitor triggers an alarm by setting the F_ADCIN bit of the STAT_1 register when the individual voltage on AINxP or AINxN exceeds the threshold set by the COMP_TH[2:0] bits. When the F_ADCIN bit of the STAT_1 register is set, indicating an out-of-range event, read the STAT_P register or STAT_N register to determine exactly which input pin exceeded the set threshold. Figure 42 shows an input overrange and underrange detection block diagram.