Figure 66 shows the relationship between DRDY, CS, SCLK, DIN, and DOUT during data retrieval in synchronous slave mode. In synchronous slave mode, the high-to-low DRDY transition sent from the processor must be synchronized with the data rate programmed, or multiples thereof, to avoid a digital filter reset. The data frame begins with a high-to-low CS transition with or after DRDY transitions low. The DIN and DOUT signals transition on the SCLK rising edge. DRDY can return high at any point but must maintain a high-to-low transition at the set data rate to avoid a resynchronization event. To minimize interface lines, the CS signal can be tied directly to the DRDY signal; the timing specifications in the Timing Requirements: Synchronous Slave Interface Mode table are still maintained.