DRDY indicates when a new conversion result is ready for retrieval. When DRDY transitions from high to low, new conversion data are ready. The DRDY signal remains low for the duration of the data frame and returns high either when CS returns high (signaling the completion of the frame), or prior to new data being available. The high-to-low DRDY transition occurs at the set data rate regardless of the CS state. If data are not completely shifted out when new data are ready, the DRDY signal toggles high for a duration of 0.5 × tMOD and back low. The device sets the F_DRDY bit in the STAT_1 register indicating that the DOUT output shift register is not updated with the new conversion result. Figure 61 shows an example of new data being ready before previous data are shifted out, causing the new conversion result to be lost. The DRDY pin is always actively driven, even when CS is high.