SBAS949A February   2020  – February 2021 ADS131M06


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Noise Measurements
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input ESD Protection Circuitry
      2. 8.3.2  Input Multiplexer
      3. 8.3.3  Programmable Gain Amplifier (PGA)
      4. 8.3.4  Voltage Reference
      5. 8.3.5  Clocking and Power Modes
      6. 8.3.6  ΔΣ Modulator
      7. 8.3.7  Digital Filter
        1. Digital Filter Implementation
          1. Fast-Settling Filter
          2. SINC3 and SINC3 + SINC1 Filter
        2. Digital Filter Characteristic
      8. 8.3.8  DC Block Filter
      9. 8.3.9  Internal Test Signals
      10. 8.3.10 Channel Phase Calibration
      11. 8.3.11 Calibration Registers
      12. 8.3.12 Communication Cyclic Redundancy Check (CRC)
      13. 8.3.13 Register Map CRC
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
        1. Power-On Reset
        2. SYNC/RESET Pin
        3. RESET Command
      2. 8.4.2 Fast Startup Behavior
      3. 8.4.3 Conversion Modes
        1. Continuous-Conversion Mode
        2. Global-Chop Mode
      4. 8.4.4 Power Modes
      5. 8.4.5 Standby Mode
      6. 8.4.6 Current-Detect Mode
    5. 8.5 Programming
      1. 8.5.1 Interface
        1.  Chip Select (CS)
        2.  Serial Data Clock (SCLK)
        3.  Serial Data Input (DIN)
        4.  Serial Data Output (DOUT)
        5.  Data Ready (DRDY)
        6.  Conversion Synchronization or System Reset (SYNC/RESET)
        7.  SPI Communication Frames
        8.  SPI Communication Words
        9.  ADC Conversion Data
          1. Collecting Data for the First Time or After a Pause in Data Collection
        10. Commands
          1. NULL (0000 0000 0000 0000)
          2. RESET (0000 0000 0001 0001)
          3. STANDBY (0000 0000 0010 0010)
          4. WAKEUP (0000 0000 0011 0011)
          5. LOCK (0000 0101 0101 0101)
          6. UNLOCK (0000 0110 0110 0110)
          7. RREG (101a aaaa annn nnnn)
            1. Reading a Single Register
            2. Reading Multiple Registers
          8. WREG (011a aaaa annn nnnn)
        11. Short SPI Frames
      2. 8.5.2 Synchronization
    6. 8.6 Registers
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Unused Inputs and Outputs
      2. 9.1.2 Antialiasing
      3. 9.1.3 Minimum Interface Connections
      4. 9.1.4 Power Metrology Applications
      5. 9.1.5 Multiple Device Configuration
      6. 9.1.6 Code Example
      7. 9.1.7 Troubleshooting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Voltage Measurement Front-End
        2. Current Measurement Front-End
        3. ADC Setup
        4. Calibration
        5. Formulae
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 CAP Pin Behavior
    2. 10.2 Power-Supply Sequencing
    3. 10.3 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Data Ready (DRDY)

The DRDY pin is an active low output that indicates when new conversion data are ready in conversion mode or that the requirements are met for current detection when in current-detect mode. Connect the DRDY pin to a digital input on the host to trigger periodic data retrieval in conversion mode.

The timing of DRDY with respect to the sampling of a given channel on the ADS131M06 depends on the phase calibration setting of the channel and the state of the DRDY_SEL[1:0] bits in the MODE register. Setting the DRDY_SEL[1:0] bits to 00b configures DRDY to assert when the channel with the largest positive phase calibration setting, or the most lagging, has a new conversion result. When the bits are 01b, the device asserts DRDY each time any channel data are ready. Finally, setting the bits to either 10b or 11b configures the device to assert DRDY when the channel with the most negative phase calibration setting, or the most leading, has new conversion data. Changing the DRDY_SEL[1:0] bits has no effect on DRDY behavior in global-chop mode because phase calibration is automatically disabled in global-chop mode.

The timing of the first DRDY assertion after channels are enabled or after a synchronization pulse is provided depends on the phase calibration setting. If the channel that causes DRDY to assert has a phase calibration setting less than zero, the first DRDY assertion can be less than one sample period from the channel being enabled or the occurrence of the synchronization pulse. However, DRDY asserts in the next sample period if the phase setting puts the output timing too close to the beginning of the sample period.

Table 8-9 lists the phase calibration setting boundary at which DRDY either first asserts within a sample period, or in the next sample period. If the setting for the channel configured to control DRDY assertion is greater than the value listed in Table 8-9 for each OSR, DRDY asserts for the first time within a sample period of the channel being enabled or the synchronization pulse. If the phase setting value is equal to or more negative than the value in Table 8-9, DRDY asserts in the following sample period. See the Section 8.5.2 section for more information about synchronization.

Table 8-9 Phase Setting First DRDY Assertion Boundary
128 –19 3EDh
256 –83 3ADh
512 –211 32Dh
1024 –467 22Dh
>1024 None N/A

The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default the bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY behaves like an open-drain digital output. Use a 100-kΩ pullup resistor to pull the pin high when DRDY is not asserted.

The DRDY_FMT bit in the MODE register determines the format of the DRDY signal. When the bit is 0b, new data are indicated by DRDY changing from high to low and remaining low until either all of the conversion data are shifted out of the device, or remaining low and going high briefly before the next time DRDY transitions low. When the DRDY_FMT bit is 1b, new data are indicated by a short negative pulse on the DRDY pin. If the host does not read conversion data after the DRDY pulse when DRDY_FMT is 1b, the device skips a conversion result and does not provide another DRDY pulse until the second following instance when data are ready because of how the pulse is generated. See the Section section for more information about the behavior of DRDY when data are not consistently read.

The DRDY pulse is blocked when new conversions complete while conversion data are read. Therefore, avoid reading ADC data during the time where new conversions complete in order to achieve consistent DRDY behavior.