SPRSPA7C September   2024  – July 2025 AM2612 , AM2612-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
    1. 3.1 Functional Block Diagram
  5. 4 Package Comparison
    1. 4.1 Device Identification
    2. 4.2 Related Products
  6. 5 Terminal Configuration and Functions
    1. 5.1 Pin Diagram
      1. 5.1.1 AM261x ZCZ Pin Diagram
      2. 5.1.2 AM261x ZFG Pin Diagram
      3. 5.1.3 AM261x ZEJ Pin Diagram
      4. 5.1.4 AM261x ZNC Pin Diagram
    2. 5.2 Pin Attributes
      1.      16
      2.      17
    3. 5.3 Signal Descriptions
      1.      19
      2. 5.3.1  ADC
        1.       21
        2.       22
        3.       23
        4. 5.3.1.1 ADC-CMPSS Signal Connections
      3. 5.3.2  ADC_CAL
        1.       26
      4. 5.3.3  ADC VREF
        1.       28
      5. 5.3.4  CPSW
        1.       30
        2.       31
        3.       32
        4.       33
        5.       34
        6.       35
        7.       36
      6. 5.3.5  CPTS
        1.       38
      7. 5.3.6  DAC
        1.       40
      8. 5.3.7  EPWM
        1.       42
        2.       43
        3.       44
        4.       45
        5.       46
        6.       47
        7.       48
        8.       49
        9.       50
        10.       51
      9. 5.3.8  EQEP
        1.       53
        2.       54
      10. 5.3.9  FSI
        1.       56
        2.       57
      11. 5.3.10 GPIO
        1.       59
      12. 5.3.11 GPMC0
        1.       61
      13. 5.3.12 I2C
        1.       63
        2.       64
        3.       65
      14. 5.3.13 LIN
        1.       67
        2.       68
        3.       69
      15. 5.3.14 MCAN
        1.       71
        2.       72
      16. 5.3.15 MMC
        1.       74
      17. 5.3.16 OSPI
        1.       76
        2.       77
      18. 5.3.17 Power Supply
        1.       79
      19. 5.3.18 PRU-ICSS
        1.       81
        2.       82
        3.       83
        4.       84
        5.       85
      20. 5.3.19 SDFM
        1.       87
        2.       88
      21. 5.3.20 SPI
        1.       90
        2.       91
        3.       92
        4.       93
      22. 5.3.21 System and Miscellaneous
        1. 5.3.21.1 Boot Mode Configuration
          1.        96
        2. 5.3.21.2 Clocking
          1.        98
          2.        99
          3.        100
        3. 5.3.21.3 Emulation and Debug
          1.        102
          2.        103
        4. 5.3.21.4 SYSTEM
          1.        105
        5. 5.3.21.5 VMON
          1.        107
        6. 5.3.21.6 Reserved
          1.        109
        7.       110
          1.        111
      23. 5.3.22 UART
        1.       113
        2.       114
        3.       115
        4.       116
        5.       117
        6.       118
      24. 5.3.23 USB0
        1.       120
      25. 5.3.24 XBAR
        1.       122
        2.       123
    4. 5.4 Pin Connectivity Requirements
      1.      Pin Connectivity Requirements
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Electrostatic Discharge (ESD) Extended Automotive Ratings
    3. 6.3  Electrostatic Discharge (ESD) Industrial Ratings
    4. 6.4  Power-On Hours (POH) Summary
      1. 6.4.1 Automotive Temperature Profile
    5. 6.5  Recommended Operating Conditions
    6. 6.6  Operating Performance Points
    7. 6.7  Power Consumption Summary
      1. 6.7.1 Power Consumption - Maximum for R5F at 400MHz
      2. 6.7.2 Power Consumption - Maximum for R5F at 500MHz
    8. 6.8  Electrical Characteristics
      1. 6.8.1 Digital and Analog IO Electrical Characteristics
      2. 6.8.2 Analog to Digital Converter Characteristics
        1. 6.8.2.1 Analog-to-Digital Converter (ADC)
        2. 6.8.2.2 ADC Input Model
      3. 6.8.3 Comparator Subsystem A (CMPSSA)
      4. 6.8.4 Digital-to-Analog Converter (DAC)
      5. 6.8.5 Power Management Unit (PMU)
      6. 6.8.6 Safety Comparators
    9. 6.9  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 6.9.1 VPP Specifications
      2. 6.9.2 Hardware Requirements
      3. 6.9.3 Programming Sequence
      4. 6.9.4 Impact to Your Hardware Warranty
    10. 6.10 Thermal Resistance Characteristics
      1. 6.10.1 ZCZ Package Thermal Characteristics
      2. 6.10.2 ZFG Package Thermal Characteristics
      3. 6.10.3 ZEJ Package Thermal Characteristics
      4. 6.10.4 ZNC Package Thermal Characteristics
    11. 6.11 Timing and Switching Characteristics
      1. 6.11.1 Timing Parameters and Information
      2. 6.11.2 Power Supply Sequencing
        1. 6.11.2.1 Power-On and Reset Sequencing
          1. 6.11.2.1.1 Power Reset Sequence Description
        2. 6.11.2.2 Power-Down Sequencing
      3. 6.11.3 System Timing
        1. 6.11.3.1 System Timing Conditions
        2. 6.11.3.2 Reset Timing
          1. 6.11.3.2.1 PORz Timing Requirements
          2.        166
          3. 6.11.3.2.2 WARMRSTn Switching Characteristics
          4.        168
          5. 6.11.3.2.3 WARMRSTn Timing Requirements
          6.        170
        3. 6.11.3.3 Safety Signal Timing
          1. 6.11.3.3.1 SAFETY_ERRORn Switching Characteristics
          2.        173
      4. 6.11.4 Clock Specifications
        1. 6.11.4.1 Input Clocks / Oscillators
          1. 6.11.4.1.1 Crystal Oscillator (XTAL) Parameters
          2. 6.11.4.1.2 External Clock Characteristics
        2. 6.11.4.2 Clock Timing
          1. 6.11.4.2.1 Clock Timing Requirements
          2.        180
          3. 6.11.4.2.2 Clock Switching Characteristics
          4.        182
      5. 6.11.5 Peripherals
        1. 6.11.5.1  3-port Gigabit Ethernet MAC (CPSW)
          1. 6.11.5.1.1 CPSW MDIO Timing
            1. 6.11.5.1.1.1 CPSW MDIO Timing Conditions
            2. 6.11.5.1.1.2 CPSW MDIO Timing Requirements
            3. 6.11.5.1.1.3 CPSW MDIO Switching Characteristics
            4.         189
          2. 6.11.5.1.2 CPSW RGMII Timing
            1. 6.11.5.1.2.1 CPSW RGMII Timing Conditions
            2. 6.11.5.1.2.2 CPSW RGMII[x]_RCLK Timing Requirements - RGMII Mode
            3. 6.11.5.1.2.3 CPSW RGMII[x]_RD[3:0], and RGMII[x]_RCTL Timing Requirements
            4.         194
            5. 6.11.5.1.2.4 CPSW RGMII[x]_TCLK Switching Characteristics - RGMII Mode
            6. 6.11.5.1.2.5 CPSW RGMII[x]_TD[3:0], and RGMII[x]_TCTL Switching Characteristics - RGMII Mode
            7.         197
          3. 6.11.5.1.3 CPSW RMII Timing
            1. 6.11.5.1.3.1 CPSW RMII Timing Conditions
            2. 6.11.5.1.3.2 CPSW RMII[x]_REFCLK Timing Requirements - RMII Mode
            3.         201
            4. 6.11.5.1.3.3 CPSW RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER Timing Requirements - RMII Mode
            5.         203
            6. 6.11.5.1.3.4 CPSW RMII[x]_TXD[1:0], and RMII[x]_TXEN Switching Characteristics - RMII Mode
            7.         205
        2. 6.11.5.2  Enhanced Capture (eCAP)
          1. 6.11.5.2.1 ECAP Timing Conditions
          2. 6.11.5.2.2 ECAP Timing Requirements
          3.        209
          4. 6.11.5.2.3 ECAP Switching Characteristics
          5.        211
        3. 6.11.5.3  Enhanced Pulse Width Modulation (ePWM)
          1. 6.11.5.3.1 EPWM Timing Conditions
          2. 6.11.5.3.2 EPWM Timing Requirements
          3.        215
          4. 6.11.5.3.3 EPWM Switching Characteristics
          5.        217
          6.        EPWM Characteristics
        4. 6.11.5.4  Enhanced Quadrature Encoder Pulse (eQEP)
          1. 6.11.5.4.1 EQEP Timing Conditions
          2. 6.11.5.4.2 EQEP Timing Requirements
          3.        222
          4. 6.11.5.4.3 EQEP Switching Characteristics
        5. 6.11.5.5  Fast Serial Interface (FSI)
          1. 6.11.5.5.1 FSI Timing Conditions
          2. 6.11.5.5.2 FSIRX Timing Requirements
          3.        227
          4. 6.11.5.5.3 FSIRX Switching Characteristics
          5. 6.11.5.5.4 FSITX Switching Characteristics
          6.        230
          7. 6.11.5.5.5 FSITX SPI Signaling Mode Switching Characteristics
          8.        232
        6. 6.11.5.6  General Purpose Input/Output (GPIO)
          1. 6.11.5.6.1 GPIO Timing Conditions
          2. 6.11.5.6.2 GPIO Timing Requirements
          3. 6.11.5.6.3 GPIO Switching Characteristics
        7. 6.11.5.7  General Purpose Memory Controller (GPMC)
          1. 6.11.5.7.1 GPMC Timing Conditions
          2. 6.11.5.7.2 GPMC/NOR Flash Timing Requirements - Synchronous Mode 100MHz
          3. 6.11.5.7.3 GPMC/NOR Flash Switching Characteristics - Synchronous Mode 100MHz
          4.        241
          5. 6.11.5.7.4 GPMC/NOR Flash Timing Requirements - Asynchronous Mode 100MHz
          6. 6.11.5.7.5 GPMC/NOR Flash Switching Characteristics - Asynchronous Mode 100MHz
          7.        244
          8. 6.11.5.7.6 GPMC/NAND Flash Timing Requirements - Asynchronous Mode 100MHz
          9. 6.11.5.7.7 GPMC/NAND Flash Switching Characteristics - Asynchronous Mode 100MHz
          10.        247
        8. 6.11.5.8  Inter-Integrated Circuit (I2C)
          1. 6.11.5.8.1 I2C
        9. 6.11.5.9  Local Interconnect Network (LIN)
          1. 6.11.5.9.1 LIN Timing Conditions
          2. 6.11.5.9.2 LIN Timing Requirements
          3. 6.11.5.9.3 LIN Switching Characteristics
        10. 6.11.5.10 Modular Controller Area Network (MCAN)
          1. 6.11.5.10.1 MCAN Timing Conditions
          2. 6.11.5.10.2 MCAN Switching Characteristics
        11. 6.11.5.11 Serial Peripheral Interface (SPI)
          1. 6.11.5.11.1 SPI Timing Conditions
          2. 6.11.5.11.2 SPI Controller Mode Timing Requirements
          3.        260
          4. 6.11.5.11.3 SPI Controller Mode Switching Characteristics (Clock Phase = 0)
          5.        262
          6. 6.11.5.11.4 SPI Peripheral Mode Timing Requirements
          7.        264
          8. 6.11.5.11.5 SPI Peripheral Mode Switching Characteristics
          9.        266
        12. 6.11.5.12 Multi-Media Card/Secure Digital (MMCSD)
          1. 6.11.5.12.1 MMC Timing Conditions
          2. 6.11.5.12.2 MMC Timing Requirements - SD Card Default Speed Mode
          3.        270
          4. 6.11.5.12.3 MMC Switching Characteristics - SD Card Default Speed Mode
          5.        272
          6. 6.11.5.12.4 MMC Timing Requirements - SD Card High Speed Mode
          7.        274
          8. 6.11.5.12.5 MMC Switching Characteristics - SD Card High Speed Mode
          9.        276
        13. 6.11.5.13 Octal Serial Peripheral Interface (OSPI)
          1. 6.11.5.13.1 OSPI Timing Conditions
          2. 6.11.5.13.2 OSPI PHY Mode
            1. 6.11.5.13.2.1 OSPI With PHY Data Training
              1. 6.11.5.13.2.1.1 OSPI DLL Delay Mapping for PHY Data Training
              2. 6.11.5.13.2.1.2 OSPI Timing Requirements - PHY Data Training
              3.          283
              4. 6.11.5.13.2.1.3 OSPI Switching Characteristics - PHY Data Training
              5.          285
            2. 6.11.5.13.2.2 OSPI0 Without Data Training
              1. 6.11.5.13.2.2.1 OSPI0 PHY SDR Timing
                1. 6.11.5.13.2.2.1.1 OSPI0 DLL Delay Mapping for PHY SDR Timing Modes
                2. 6.11.5.13.2.2.1.2 OSPI0 Timing Requirements - PHY SDR Mode
                3.           290
                4. 6.11.5.13.2.2.1.3 OSPI0 Switching Characteristics - PHY SDR Mode
                5.           292
              2. 6.11.5.13.2.2.2 OSPI0 PHY DDR Timing
                1. 6.11.5.13.2.2.2.1 OSPI0 DLL Delay Mapping for PHY DDR Timing Modes
                2. 6.11.5.13.2.2.2.2 OSPI0 Timing Requirements - PHY DDR Mode
                3.           296
                4. 6.11.5.13.2.2.2.3 OSPI0 Switching Characteristics - PHY DDR Mode
                5.           298
            3. 6.11.5.13.2.3 OSPI1 Without Data Training
              1. 6.11.5.13.2.3.1 OSPI1 PHY SDR Timing
                1. 6.11.5.13.2.3.1.1 OSPI1 DLL Delay Mapping for PHY SDR Timing Modes
                2. 6.11.5.13.2.3.1.2 OSPI1 Timing Requirements - PHY SDR Mode
                3.           303
                4. 6.11.5.13.2.3.1.3 OSPI1 Switching Characteristics - PHY SDR Mode
                5.           305
              2. 6.11.5.13.2.3.2 OSPI1 PHY DDR Timing
                1. 6.11.5.13.2.3.2.1 OSPI1 DLL Delay Mapping for PHY DDR Timing Modes
                2. 6.11.5.13.2.3.2.2 OSPI1 Timing Requirements - PHY DDR Mode
                3.           309
                4. 6.11.5.13.2.3.2.3 OSPI1 Switching Characteristics - PHY DDR Mode
                5.           311
          3. 6.11.5.13.3 OSPI Tap Mode
            1. 6.11.5.13.3.1 OSPI Tap SDR Timing
              1. 6.11.5.13.3.1.1 OSPI Timing Requirements - Tap SDR Mode
              2.          315
              3. 6.11.5.13.3.1.2 OSPI Switching Characteristics - Tap SDR Mode
              4.          317
            2. 6.11.5.13.3.2 OSPI0 Tap DDR Timing
              1. 6.11.5.13.3.2.1 OSPI Timing Requirements - Tap DDR Mode
              2.          320
              3. 6.11.5.13.3.2.2 OSPI Switching Characteristics - Tap DDR Mode
              4.          322
        14. 6.11.5.14 Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS)
          1. 6.11.5.14.1 PRU-ICSS Programmable Real-Time Unit (PRU)
            1. 6.11.5.14.1.1 PRU-ICSS PRU Timing Conditions
            2. 6.11.5.14.1.2 PRU-ICSS PRU Switching Characteristics - Direct Output Mode
            3.         327
            4. 6.11.5.14.1.3 PRU-ICSS PRU Timing Requirements - Parallel Capture Mode
            5.         329
            6. 6.11.5.14.1.4 PRU-ICSS PRU Timing Requirements - Shift In Mode
            7.         331
            8. 6.11.5.14.1.5 PRU-ICSS PRU Switching Characteristics - Shift Out Mode
            9.         333
          2. 6.11.5.14.2 PRU-ICSS PRU Sigma Delta and Peripheral Interface
            1. 6.11.5.14.2.1 PRU-ICSS PRU Sigma Delta and Peripheral Interface Timing Conditions
            2. 6.11.5.14.2.2 PRU-ICSS PRU Timing Requirements - Sigma Delta Mode
            3.         337
            4. 6.11.5.14.2.3 PRU-ICSS PRU Timing Requirements - Peripheral Interface Mode
            5.         339
            6. 6.11.5.14.2.4 PRU-ICSS PRU Switching Characteristics - Peripheral Interface Mode
            7.         341
          3. 6.11.5.14.3 PRU-ICSS Pulse Width Modulation (PWM)
            1. 6.11.5.14.3.1 PRU-ICSS PWM Timing Conditions
            2. 6.11.5.14.3.2 PRU-ICSS PWM Switching Characteristics
            3.         345
          4. 6.11.5.14.4 PRU-ICSS Industrial Ethernet Peripheral (IEP)
            1. 6.11.5.14.4.1 PRU-ICSS IEP Timing Conditions
            2. 6.11.5.14.4.2 PRU-ICSS IEP Timing Requirements - Input Validated with SYNCx
            3.         349
            4. 6.11.5.14.4.3 PRU-ICSS IEP Timing Requirements - Digital IOs
            5.         351
            6. 6.11.5.14.4.4 PRU-ICSS IEP Timing Requirements - LATCHx_IN
            7.         353
          5. 6.11.5.14.5 PRU-ICSS Universal Asynchronous Receiver Transmitter (UART)
            1. 6.11.5.14.5.1 PRU-ICSS UART Timing Conditions
            2. 6.11.5.14.5.2 PRU-ICSS UART Timing Requirements
            3. 6.11.5.14.5.3 PRU-ICSS UART Switching Characteristics
            4.         358
          6. 6.11.5.14.6 PRU-ICSS Enhanced Capture Peripheral (ECAP)
            1. 6.11.5.14.6.1 PRU-ICSS ECAP Timing Conditions
            2. 6.11.5.14.6.2 PRU-ICSS ECAP Timing Requirements
            3.         362
            4. 6.11.5.14.6.3 PRU-ICSS ECAP Switching Characteristics
            5.         364
          7. 6.11.5.14.7 PRU-ICSS MDIO and MII
            1. 6.11.5.14.7.1 PRU-ICSS MDIO Timing
              1. 6.11.5.14.7.1.1 PRU-ICSS MDIO Timing Conditions
              2. 6.11.5.14.7.1.2 PRU-ICSS MDIO Timing Requirements
              3. 6.11.5.14.7.1.3 PRU-ICSS MDIO Switching Characteristics
              4.          370
            2. 6.11.5.14.7.2 PRU-ICSS MII Timing
              1. 6.11.5.14.7.2.1 PRU-ICSS MII Timing Conditions
              2. 6.11.5.14.7.2.2 PRU-ICSS MII Timing Requirements - MII[x]_RX_CLK
              3.          374
              4. 6.11.5.14.7.2.3 PRU-ICSS MII Timing Requirements - MII[x]_RXD[3:0], MII[x]_RX_DV, and MII[x]_RX_ER
              5.          376
              6. 6.11.5.14.7.2.4 PRU-ICSS MII Switching Characteristics - MII[x]_TX_CLK
              7.          378
              8. 6.11.5.14.7.2.5 PRU-ICSS MII Switching Characteristics - MII[x]_TXD[3:0] and MII[x]_TXEN
              9.          380
        15. 6.11.5.15 Sigma Delta Filter Module (SDFM)
          1. 6.11.5.15.1 SDFM Timing Conditions
          2. 6.11.5.15.2 SDFM Switching Characteristics
        16. 6.11.5.16 Universal Asynchronous Receiver/Transmitter (UART)
          1. 6.11.5.16.1 UART Timing Conditions
          2. 6.11.5.16.2 UART Timing Requirements
          3. 6.11.5.16.3 UART Switching Characteristics
          4.        388
        17. 6.11.5.17 Universal Serial Bus (USB)
      6. 6.11.6 Emulation and Debug
        1. 6.11.6.1 JTAG
          1. 6.11.6.1.1 JTAG Timing Conditions
          2. 6.11.6.1.2 JTAG Timing Requirements
          3. 6.11.6.1.3 JTAG Switching Characteristics
          4.        395
        2. 6.11.6.2 Trace
          1. 6.11.6.2.1 Debug Trace Timing Conditions
          2. 6.11.6.2.2 Debug Trace Switching Characteristics
          3.        399
    12. 6.12 Decoupling Capacitor Requirements
      1. 6.12.1 Decoupling Capacitor Requirements
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Processor Subsystems
      1. 7.2.1 Arm Cortex-R5F Subsystem
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Device Connection and Layout Fundamentals
      1. 8.1.1 External Oscillator
      2. 8.1.2 JTAG, EMU, and TRACE
      3. 8.1.3 Hardware Reference Design and Guidelines
      4. 8.1.4 USB 2.0 Operation
    2. 8.2 OSPI Reset
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Table 5-31 GPIO Signal Descriptions
Signal Name [1] Pin Type [2] Description [3] ZCZ PIN [4] ZFG PIN [4] ZEJ PIN [4] ZNC PIN [4]
GPIO0 IO General Purpose Input/Output P1 U4 N3 R1
GPIO1 IO General Purpose Input/Output R3 T2 M3 R2
GPIO2 IO General Purpose Input/Output N2 M3 L2 M2
GPIO3 (1) IO General Purpose Input/Output (SOP0) N1 R2 M2 N2
GPIO4 (2) IO General Purpose Input/Output (SOP1) N4 R1 N1 N1
GPIO5 IO General Purpose Input/Output M4 T1 L3 P2
GPIO6 IO General Purpose Input/Output P3 U1 N2 P1
GPIO7 IO General Purpose Input/Output M1 P1 J3 K2
GPIO8 IO General Purpose Input/Output L1 P2 K1 L1
GPIO9 IO General Purpose Input/Output L2 N2 K2 J2
GPIO10 IO General Purpose Input/Output K1 N1 J2 K1
GPIO11 IO General Purpose Input/Output C11 B13 B11 C13
GPIO12 (5) IO General Purpose Input/Output (SOP2) A11 A13 A12 A12
GPIO13 (6) IO General Purpose Input/Output (SOP3) C10 B12 A10 B12
GPIO14 IO General Purpose Input/Output B11 C12 A11 B11
GPIO15 IO General Purpose Input/Output C9 D11 B9
GPIO16 IO General Purpose Input/Output A10 A12 B10
GPIO17 IO General Purpose Input/Output B10 D10 A9
GPIO18 IO General Purpose Input/Output D9 C9 C11
GPIO19 IO General Purpose Input/Output A9 A11 C10 A11
GPIO100 IO General Purpose Input/Output M15 P19 J16 N19
GPIO101 IO General Purpose Input/Output H17 K20 F15 H19
GPIO102 IO General Purpose Input/Output H16 L19 G14 H18
GPIO103 IO General Purpose Input/Output F15 F20 E18
GPIO104 IO General Purpose Input/Output C18 E20
GPIO105 IO General Purpose Input/Output D17 E19
GPIO106 IO General Purpose Input/Output D18 G18 C19
GPIO107 IO General Purpose Input/Output E16 F19 E13 D19
GPIO108 IO General Purpose Input/Output F16 G19 D15 E19
GPIO109 IO General Purpose Input/Output F18 H20 D14 G18
GPIO110 IO General Purpose Input/Output G16 H19 D16 F18
GPIO111 IO General Purpose Input/Output E17 H17 E17
GPIO112 IO General Purpose Input/Output E18 G20 F19
GPIO113 IO General Purpose Input/Output C16 B20 B18
GPIO114 IO General Purpose Input/Output A17 E18 A18
GPIO115 IO General Purpose Input/Output B18 F17 D18
GPIO116 IO General Purpose Input/Output B17 D20 C18
GPIO117 IO General Purpose Input/Output D16 C20 B19
GPIO118 IO General Purpose Input/Output C17 D19 C17
GPIO119 IO General Purpose Input/Output D15 C18 B16
GPIO120 IO General Purpose Input/Output C15 C19 B17
GPIO121 IO General Purpose Input/Output P2 U2 P3 T1
GPIO122 IO General Purpose Input/Output B16 B19 C15
GPIO123 IO General Purpose Input/Output D14 C16 A15
GPIO124 IO General Purpose Input/Output A16 A19 C16
GPIO125 IO General Purpose Input/Output D13 B17 C14
GPIO126 IO General Purpose Input/Output B15 A18 B16 A17
GPIO127 IO General Purpose Input/Output C13 A17 A14 A16
GPIO128 IO General Purpose Input/Output A15 B18 B15
GPIO129 IO General Purpose Input/Output C14 D17 B14
GPIO130 IO General Purpose Input/Output B14 A16 D13 B15
GPIO131 IO General Purpose Input/Output A14 B16 C13 A15
GPIO132 IO General Purpose Input/Output C12 C14 C12 A14
GPIO133 IO General Purpose Input/Output D11 D15 B13 B14
GPIO134 (4) IO General Purpose Input/Output B13 B15 B12 B13
GPIO135 (3) IO General Purpose Input/Output A13 A15 A13 A13
GPIO136 IO General Purpose Input/Output B12 B14
GPIO137 IO General Purpose Input/Output A12 A14
GPIO138 IO General Purpose Input/Output M2 M1 H1 J3
GPIO139 IO General Purpose Input/Output V2 V1 R1 V1
GPIO140 IO General Purpose Input/Output U3 W1 P1 U1
GPIO20 IO General Purpose Input/Output B9 B11 D8 B10
GPIO21 IO General Purpose Input/Output B8 B10 B8 A10
GPIO22 IO General Purpose Input/Output A8 A10 C9 B9
GPIO23 IO General Purpose Input/Output D7 B9 B7
GPIO24 IO General Purpose Input/Output C8 A9 A8
GPIO25 IO General Purpose Input/Output C7 C7 C8 C9
GPIO26 IO General Purpose Input/Output B7 D8 A7 A9
GPIO27 IO General Purpose Input/Output A7 A8 A6 A8
GPIO28 IO General Purpose Input/Output A6 B8 B6 B8
GPIO29 IO General Purpose Input/Output R17 W20 P16 V19
GPIO30 IO General Purpose Input/Output R18 V19 M14 U17
GPIO31 IO General Purpose Input/Output U17 Y18 P14 W17
GPIO32 IO General Purpose Input/Output T17 W18 P15 V17
GPIO33 IO General Purpose Input/Output U18 Y19 R16 W18
GPIO34 IO General Purpose Input/Output T18 W19 N14 V18
GPIO35 IO General Purpose Input/Output N18 U20 L15 R18
GPIO36 IO General Purpose Input/Output M18 T20 M16 T19
GPIO37 IO General Purpose Input/Output P16 V18 N15 U18
GPIO38 IO General Purpose Input/Output P17 V20 N16 U19
GPIO39 IO General Purpose Input/Output P18 U19 L13 R17
GPIO40 IO General Purpose Input/Output N17 T19 M15 T18
GPIO41 IO General Purpose Input/Output N16 R17 L16 P18
GPIO42 IO General Purpose Input/Output M17 T18 L14 R19
GPIO43 IO General Purpose Input/Output B2 B3 A4 B5
GPIO44 IO General Purpose Input/Output B1 C3 A5 A6
GPIO45 IO General Purpose Input/Output D3 A2 B4 A5
GPIO46 IO General Purpose Input/Output D2 A3 C5 A4
GPIO47 IO General Purpose Input/Output C2 B1 A3 A3
GPIO48 IO General Purpose Input/Output C1 B2 A2 B4
GPIO49 IO General Purpose Input/Output E2 C1 B2 A2
GPIO50 IO General Purpose Input/Output E3 C2 C4 B2
GPIO51 IO General Purpose Input/Output D1 D2 B1 B1
GPIO52 IO General Purpose Input/Output E4 D1 C1 B3
GPIO53 IO General Purpose Input/Output F2 E2 C2 C2
GPIO54 IO General Purpose Input/Output G2 E1 D3 C1
GPIO55 IO General Purpose Input/Output E1 F2 E3 E3
GPIO56 IO General Purpose Input/Output F3 F1 F4 E2
GPIO57 IO General Purpose Input/Output F4 G2 D2 D2
GPIO58 IO General Purpose Input/Output F1 G1 D1 D1
GPIO59 IO General Purpose Input/Output G3 H2 E2 E1
GPIO60 IO General Purpose Input/Output H2 H1 E1 F1
GPIO61(7)(8) IO General Purpose Input/Output G1 K4 F2 F2
GPIO62 IO General Purpose Input/Output J2 L2 F3 G1
GPIO63 IO General Purpose Input/Output G4 J2
GPIO64 IO General Purpose Input/Output J3 J1
GPIO65 IO General Purpose Input/Output H1 J3
GPIO66 IO General Purpose Input/Output J1 K2 G3
GPIO67 IO General Purpose Input/Output K2 K1 G2 G2
GPIO68 IO General Purpose Input/Output J4 L4 H3 H1
GPIO69 IO General Purpose Input/Output K4 L1 H2 H2
GPIO70 IO General Purpose Input/Output K3 M2 G1 J1
GPIO71 IO General Purpose Input/Output V17 W16 R14 V15
GPIO72 IO General Purpose Input/Output T16 Y16 T14 W15
GPIO73 IO General Purpose Input/Output P15 W17 T15 W16
GPIO74 IO General Purpose Input/Output R16 Y17 R15 V16
GPIO75 IO General Purpose Input/Output L3 T3 M1 L2
GPIO76 IO General Purpose Input/Output M3 R4 L1 M1
GPIO77 IO General Purpose Input/Output B6 B7
GPIO78 IO General Purpose Input/Output A4 A6
GPIO79 IO General Purpose Input/Output B5 B6
GPIO80 IO General Purpose Input/Output B4 A5
GPIO81 IO General Purpose Input/Output A3 B5
GPIO82 IO General Purpose Input/Output A2 A4
GPIO83 IO General Purpose Input/Output C6 B4
GPIO84 IO General Purpose Input/Output A5 A7
GPIO85 IO General Purpose Input/Output L17 R19 K15 N17
GPIO86 IO General Purpose Input/Output L18 R20 K16 P19
GPIO87 IO General Purpose Input/Output G17 K19 F14 G17
GPIO88 IO General Purpose Input/Output F17 J19 E15
GPIO89 IO General Purpose Input/Output G18 J20 E16 J18
GPIO90 IO General Purpose Input/Output G15 J18 E14 G19
GPIO91 IO General Purpose Input/Output K15 N20 H15 L18
GPIO92 IO General Purpose Input/Output K16 L20 G15 J19
GPIO93 IO General Purpose Input/Output K17 N17 K14 M18
GPIO94 IO General Purpose Input/Output K18 N19 H14 L19
GPIO95 IO General Purpose Input/Output J18 M18 G16 K19
GPIO96 IO General Purpose Input/Output J17 M20 J14 L17
GPIO97 IO General Purpose Input/Output H18 M19 F16 K18
GPIO98 IO General Purpose Input/Output L16 P18 H16 M19
GPIO99 IO General Purpose Input/Output M16 P20 J15 N18
(1) The GPIO3 pin is also used as SOP0 bootmode configuration pin.
(2) The GPIO4 pin is also used as SOP1 bootmode configuration pin.
(3) GPIO135 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.
(4) GPIO134 is implemented with the I2C OD FS (Open Drain Fail Safe) voltage buffer.
(5) The GPIO12 pin is also used as SOP2 bootmode configuration pin.
(6) The GPIO13 pin is also used as SOP3 bootmode configuration pin.
(7) In OSPI boot mode, the AM261x ROM code configures GPIO61 as OSPI0_RESET_OUT0 and drives the pin low to reset an external OSPI device during this boot mode. However, due to a configuration in the OSPI controller, this pin does not de-assert after and external OSPI flash device resets, thus holding any external flash device in reset and causing the boot to fail. This means that GPIO61 is pulled high and then configured low until after boot is completed, which may affect certain applications. For more information, see the AM261x Errata Document.
(8) For additional information on OSPI flash reset, see OSPI Reset within the Applications, Implementation and Layout section.