SLUSE99C September   2021  – January 2023 BQ25180

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Battery Charging Process
        1. 8.1.1.1 Trickle Charge
        2. 8.1.1.2 Precharge
        3. 8.1.1.3 Fast Charge
        4. 8.1.1.4 Termination
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Based Dynamic Power Management (VINDPM)
      2. 8.3.2  Dynamic Power Path Management Mode (DPPM)
      3. 8.3.3  Battery Supplement Mode
      4. 8.3.4  SYS Power Control (SYS_MODE bit control)
        1. 8.3.4.1 SYS Pulldown Control
      5. 8.3.5  SYS Regulation
      6. 8.3.6  ILIM Control
      7. 8.3.7  Protection Mechanisms
        1. 8.3.7.1 Input Overvoltage Protection
        2. 8.3.7.2 Battery Undervoltage Lockout
        3. 8.3.7.3 System Overvoltage Protection
        4. 8.3.7.4 System Short Protection
        5. 8.3.7.5 Battery Overcurrent Protection
        6. 8.3.7.6 Safety Timer and Watchdog Timer
        7. 8.3.7.7 Thermal Protection and Thermal Regulation
      8. 8.3.8  Pushbutton Wake and Reset Input
        1. 8.3.8.1 Pushbutton Wake or Short Button Press Functions
        2. 8.3.8.2 Pushbutton Reset or Long Button Press Functions
      9. 8.3.9  15-Second Timeout for HW Reset
      10. 8.3.10 Hardware Reset
      11. 8.3.11 Software Reset
      12. 8.3.12 Interrupt Indicator (/INT) Pin
      13. 8.3.13 External NTC Monitoring (TS)
        1. 8.3.13.1 TS Biasing and Function
      14. 8.3.14 I2C Interface
        1. 8.3.14.1 F/S Mode Protocol
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
      1. 8.5.1 I2C Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input (IN/SYS) Capacitors
        2. 9.2.2.2 TS
        3. 9.2.2.3 Recommended Passive Components
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YBG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.12 Interrupt Indicator (/INT) Pin

The device contains an open-drain output that signals its status and is valid only after the device has completed start-up into a valid state. If the part starts into a fault, interrupts will not be sent.

The /INT pin is normally in high impedance and is pulled low for 128 μs when an interrupt condition occurs. When a fault or status change occurs or any other condition that generates an interrupt, a 128-μs pulse (/INT pin pulled down) is sent on /INT to notify the host.

Interrupts can be masked through I2C. If the interrupt condition occurs while the interrupt is masked an interrupt pulse will not be sent. If the interrupt is unmasked while the fault condition is still present, an interrupt pulse will not be sent until the /INT trigger condition occurs while unmasked. Below are a list of interrupts that can be masked through I2C.

Table 8-5 Mask Bit
MASK BITACTION

ILIM_INT_MASK

Do not issue an /INT pulse when ILIM limiting occurs

VDPM_INT_MASK

Do not issue an /INT pulse when VINDPM or DDPM is active

TS_INT_MASK

Do not issue an /INT pulse when any of the TS events have occured.

TREG_INT_MASK

Do not issue an /INT pulse when TREG is actively reducing the current

PG_INT_MASK

Do not issue an /INT pulse when VIN meets VIN_PG condition

BAT_INT_MASK

Do not issue an /INT pulse when BATOCP or BUVLO event is triggered

CHG_STATUS_INT_MASK

Do not send an interrupt anytime there is a charging status change.