SBAS649 June   2021 DAC12DL3200

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Power Consumption
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 2xRF Mode
      2. 7.3.2 DAC Output Interface
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-scale Current Adjustment
        3. 7.3.2.3 Example Analog Output Interfaces
      3. 7.3.3 LVDS Interface
        1. 7.3.3.1 MODE0: Two LVDS banks per channel
        2. 7.3.3.2 MODE1: One LVDS bank per channel
        3. 7.3.3.3 MODE2: Four LVDS banks, single channel mode
        4. 7.3.3.4 LVDS Interface Input Strobe
        5. 7.3.3.5 FIFO Operation
          1. 7.3.3.5.1 Using FIFO Delay Readback Values
          2. 7.3.3.5.2 FIFO Delay Handling
          3. 7.3.3.5.3 FIFO Delay and NCO Operation
          4. 7.3.3.5.4 FIFO Over/Under Flow Alarming
    4. 7.4 Multi-Device Synchronization (SYSREF+/-)
      1. 7.4.1 DACCLK Domain Synchronization
      2. 7.4.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
    5. 7.5 Alarms
    6. 7.6 Device Functional Modes
      1. 7.6.1 Direct Digital Synthesis (DDS) Mode
        1. 7.6.1.1 NCO Gain Scaling
        2. 7.6.1.2 NCO Phase Continuous Operation
    7. 7.7 Programming
      1. 7.7.1 Using the Serial Interface
        1. 7.7.1.1 SCS
        2. 7.7.1.2 SCLK
        3. 7.7.1.3 SDI
        4. 7.7.1.4 SDO
        5. 7.7.1.5 Serial Interface Operation
        6. 7.7.1.6 Streaming Mode
      2. 7.7.2 SPI Register Map
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure with LVDS Input
      2. 8.1.2 Startup Procedure With NCO Operation
      3. 8.1.3 Interface Test Pattern and Timing Verification
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 Power Up and Down Sequence
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ACF|256
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • 12-bit resolution
  • Maximum input and output sample rate:
    • Single channel up to 6.4 GSPS
    • Dual channel up to 3.2 GSPS
  • Multi-Nyquist operating modes:
    • Single channel modes: NRZ, RTZ, RF
    • Dual channel modes: NRZ, RTZ, RF, 2xRF
  • Low latency through device: 6 to 8 ns
  • Matching transmit capabilities to the low latency receiver ADC12DL3200
    • DAC and ADC combined latency < 15ns (not including FPGA)
  • Parallel DDR LVDS interface:
    • Source synchronous interface to simplify timing:
    • 24 or 48 LVDS pairs up to 1.6 Gbps
    • 1 LVDS DDR clock per 12-bit bus
  • Output frequency range: > 8 GHz
  • Full-scale current: 20 mA
  • Simplified clocking and synchronization
    • SYSREF windowing eases setup and hold times
  • On-chip direct digital synthesizer (DDS)
    • Single-tone and two-tone sine wave generation
    • 32x 32-bit numerically controlled oscillators
    • Fast frequency hopping capability (< 500 ns)
    • Synchronous CMOS frequency/phase input
  • Performance at fOUT = 4.703 GHz, 6.4 GSPS, RF mode
    • Output power: –3 dBm
    • Noise floor (70 MHz offset): –147 dBc/Hz
    • SFDR: 60 dBc
  • Power supplies: 1.0 V, 1.8 V, –1.8 V
  • Power consumption: 1.39 W (2-ch, RF mode, 3.2GSPS)
  • Package: 256-Ball FCBGA (17x17 mm, 1 mm pitch)